OpenCores

USB Device Core :: Overview



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Details

Name: usb_device_core
Created: Mar 26, 2014
Updated: Mar 27, 2014
SVN Updated: Apr 23, 2019
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star9you like it: star it!

Other project properties

Category:Communication controller
Language:Verilog
Development status:Alpha
Additional info:Design done, FPGA proven
WishBone compliant: Yes
WishBone version: n/a
License: LGPL

USB Peripheral Interface

Github: http://github.com/ultraembedded/cores

This component is a simple USB Peripheral Interface (Device) implementation with an AXI4-Lite slave register interface, and with a UTMI interface for connection to a USB PHY.

It has been designed to support USB2.0, but currently has been only tested in Full Speed peripheral mode (12Mbit/s).

Features
  • USB 2.0 Device mode support.
  • Simple register data read/write interface (low performance / not DMA based).
  • UTMI PHY interface (see my UTMI to ULPI Conversion wrapper project to allow connection to a ULPI PHY e.g. USB3300)
  • Current build configuration has 4 endpoints
Limitations
  • Only tested for USB-FS (Full Speed / 12Mbit/s) only.
  • AXI4-L address and data must arrive in the same cycle.
Software

Provided with a USB-CDC test stack (USB Serial port) with loopback/echo example.

To make this functional on your platform;

  • Set USB_DEV_BASE to the correct address for the peripheral.
  • Implement the millisecond timer functions in timer.h.
  • Change USB_BYTE_SWAP16 in usbf_defs.h if your CPU is big endian.
Testing

Verified under simulation then tested on FPGA as a USB-CDC mode peripheral (USB serial port) against Linux & Windows PCs.

References
Register Map
OffsetNameDescription
0x00USB_FUNC_CTRLRW Control Register
0x04USB_FUNC_STATRW Status Register
0x08USB_FUNC_ADDRRW Address Register
0x0cUSB_EP0_CFGRW Endpoint 0 Configuration
0x10USB_EP0_TX_CTRLRW Endpoint 0 Tx Control
0x14USB_EP0_RX_CTRLW Endpoint 0 Rx Control
0x18USB_EP0_STSR Endpoint 0 status
0x1cUSB_EP0_DATARW Endpoint Data FIFO
0x20USB_EP1_CFGRW Endpoint 1 Configuration
0x24USB_EP1_TX_CTRLRW Endpoint 1 Tx Control
0x28USB_EP1_RX_CTRLW Endpoint 1 Rx Control
0x2cUSB_EP1_STSR Endpoint 1 status
0x30USB_EP1_DATARW Endpoint Data FIFO
0x34USB_EP2_CFGRW Endpoint 2 Configuration
0x38USB_EP2_TX_CTRLRW Endpoint 2 Tx Control
0x3cUSB_EP2_RX_CTRLW Endpoint 2 Rx Control
0x40USB_EP2_STSR Endpoint 2 status
0x44USB_EP2_DATARW Endpoint Data FIFO
0x48USB_EP3_CFGRW Endpoint 3 Configuration
0x4cUSB_EP3_TX_CTRLRW Endpoint 3 Tx Control
0x50USB_EP3_RX_CTRLW Endpoint 3 Rx Control
0x54USB_EP3_STSR Endpoint 3 status
0x58USB_EP3_DATARW Endpoint Data FIFO
Register: USB_FUNC_CTRL
BitsNameDescription
8HS_CHIRP_ENHigh-speed Chirp Enable
7PHY_DMPULLDOWNUTMI PHY D+ Pulldown Enable
6PHY_DPPULLDOWNUTMI PHY D+ Pulldown Enable
5PHY_TERMSELECTUTMI PHY Termination Select
4:3PHY_XCVRSELECTUTMI PHY Transceiver Select
2:1PHY_OPMODEUTMI PHY Output Mode
0INT_EN_SOFInterrupt enable - SOF reception
Register: USB_FUNC_STAT
BitsNameDescription
13RSTUSB Reset Detected (cleared on write)
12:11LINESTATEUSB line state (bit 1 = D+, bit 0 = D-)
10:0FRAMEFrame number
Register: USB_FUNC_ADDR
BitsNameDescription
6:0DEV_ADDRDevice address
Register: USB_EPx_CFG
BitsNameDescription
3INT_RXInterrupt on Rx ready
2INT_TXInterrupt on Tx complete
1STALL_EPStall endpoint
0ISOIsochronous endpoint
Register: USB_EPx_TX_CTRL
BitsNameDescription
17TX_FLUSHInvalidate Tx buffer
16TX_STARTTransmit start - enable transmit of endpoint data
10:0TX_LENTransmit length
Register: USB_EPx_RX_CTRL
BitsNameDescription
1RX_FLUSHInvalidate Rx buffer
0RX_ACCEPTReceive data accepted (read)
Register: USB_EPx_STS
BitsNameDescription
20TX_ERRTransmit error (buffer underrun)
19TX_BUSYTransmit busy (active)
18RX_ERRReceive error - CRC mismatch or buffer overflow
17RX_SETUPSETUP request received
16RX_READYReceive ready (data available)
10:0RX_COUNTEndpoint received length (RD)
Register: USB_EPx_DATA
BitsNameDescription
7:0DATARead or write from Rx or Tx endpoint FIFO