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USB Device Core :: Overview



Project maintainers

Details

Name: usb_device_core
Created: Mar 26, 2014
Updated: Mar 27, 2014
SVN Updated: Mar 27, 2014
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star5you like it: star it!

Other project properties

Category:Communication controller
Language:Verilog
Development status:Alpha
Additional info:Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

A simple full speed USB device core with 4 endpoints.
Comes with virtual COM port demo sw.

More details to follow.
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