Fixed Point Math Library for Verilog
Hi, I was using the code of qmult.v The sign bit is not assigned correctly if we multiply a negative number by 0. Ideally the sign bit should be '0'. But the xor of the 2 sign bits (1 ^ 0) gives an incorrect value of 1.
I am sorry for opening the bug.. 1000 & 0000 are both valid for representing a '0' for a 4-bit number with sign+magnitude format.
Please close the bug.
BTW, Is there a similar library for doing fixed-point multiplication with 2's complement number format?
It is correct to have a negative and positive zero in mathematical operations. Imagine, that we performed a multiply by a very small number that essentially caused an underflow (which my modules do not detect). The "ghost" of this number would be only its sign, as it would otherwise be all zeroes in its representation.
This is important for multiple reasons: First, other mathematical functions have definitions based on the sign of zero (logarithms, for instance). second, this keeps an underflow from having the wrong sign in certain applications.
I believe this should stay, and was something I considered when I wrote the module.
As for the question RE: similar library - no, not that I know of. Certainly not by me.
PS: more on this here: http://www.johndcook.com/blog/2010/06/15/why-computers-have-signed-zero/