Name: verilog_fixed_point_math_library

Created: Jan 3, 2014

Updated: Feb 14, 2019

SVN Updated: May 26, 2014

SVN: Browse

Latest version: download (might take a bit to start...)

Statistics: View

Bugs: 2 reported / 1 solved

Created: Jan 3, 2014

Updated: Feb 14, 2019

SVN Updated: May 26, 2014

SVN: Browse

Latest version: download (might take a bit to start...)

Statistics: View

Bugs: 2 reported / 1 solved

Star15you like it: star it!

Category:Arithmetic core

Language:Verilog

Development status:Mature

Additional info:Design done, FPGA proven, Specification done

WishBone compliant: No

WishBone version: n/a

License: LGPL

Language:Verilog

Development status:Mature

Additional info:Design done, FPGA proven, Specification done

WishBone compliant: No

WishBone version: n/a

License: LGPL

Hey, this project has been downloaded many, *many* times it would seem. I'm glad you've found it useful. I would be interested in who (and where) the users are, and what the use is (some project, school, hobby, etc). If you use the library, would you be so kind as to drop me a note? Don't expect a response, just for my own edification.

Thanks,*Tom*

Verilog Fixed point math library

Original work by Sam Skalicky, originally found here

Extended, updated, and heavily commented by Tom Burke

This library includes the basic math functions for the Verilog Language,

for implementation on FPGAs.

All units have been simulated and synthesized for Xilinx Spartan 3E devices

using the Xilinx ISE WebPack tools v14.7

These math routines use a signed magnitude Q,N format, where N is the total

number of bits used, and Q is the number of fractional bits used. For instance,

15,32 would represent a 32-bit number with 15 fractional bits, 16 integer bits,

and 1 sign bit as shown below:

|1||| |S|IIIIIIIIIIIIIIII|FFFFFFFFFFFFFFF|

This library contains the following modules:

qadd.v - Addition module; adds 2 numbers of any sign. qdiv.v - Division module; divides two numbers using a right-shift and subtract algorithm - requires an input clock qmult.v - Multiplication module; purely combinational for systems that will support it qmults.v - Multiplication module; uses a left-shift and add algorithm - requires an input clock (for systems that cannot support the synthesis of a combinational multiplier) Test_add.v - Test fixture for the qadd.v module Test_mult.v - Test fixture for the qmult.v module TestDiv.v - Test fixture for the qdiv.v module TestMultS.v - Test fixture for the qmults.v module

These math routines default to a (Q,N) of (15,32), but are easily customizable

to your application by changing their input parameters. For instance, an

unmodified use of (15,32) would look something like this:

qadd my_adder( .a(addend_a), .b(addend_b), .c(result) );

To change this to an (8,23) notation, for instance, the same module would be

instantiated thusly:

qadd #(8,23) my_adder( .a(addend_a), .b(addend_b), .c(result) );

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