Fixed Point Math Library for Verilog

Hi ,

The qdiv module doesnt give the expected result. I am having a and b of width (Q,N) as (16,32). Quartus throws a warning saying,

Warning (10230): Verilog HDL assignment warning at qdiv.v(95): truncated value with size 78 to match size of target (47) Warning (10230): Verilog HDL assignment warning at qdiv.v(101): truncated value with size 78 to match size of target (32)

I am getting qout as zero.

I have no experience with the Quartus stuff - I've only tested with Xilinx tools.

However, this would seem to not be a problem with the code itself, but with a mismatch of something you're interfacing to. The message about a truncated value would seem to indicate that that interfacing component is a different size, and that there's a possibility that you're losing data.

Have you tried simulating your module?