Erlandsson, Marcus

Unneback, Michael

Versatile FIFO

## Introduction

![sync-fifo](/usercontent/img/1240397998)

The FIFO implementation outlined in this document can easily be configured to suit the following

-   asynchronous FIFO with different clock domains for read and write sides
-   synchronous FIFO with programmable flags
-   multiple FIFO sharing the same memory resource

This FIFO can easily be extended to have common wishbone interface for all individual FIFO channels.


<h2 id="introduction">Introduction</h2>
<p><img src="/usercontent/img/1240397998" alt="sync-fifo" width="600" height="300" />
<p> The FIFO implementation outlined in this document can easily be configured to suit the following 
</p>
<ul>
<li>asynchronous FIFO with different clock domains for read and write sides</li>
<li>synchronous FIFO with programmable flags</li>
<li>multiple FIFO sharing the same memory resource</li>
</ul>
<p>
This FIFO can easily be extended to have common wishbone interface for all individual FIFO channels.
</p></p>


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Versatile FIFO

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