VIIRF - Versatile IIR Filter
Project maintainers
Details
Name: viirf
Created: Jun 5, 2017
Updated: Jun 5, 2017
SVN Updated: Nov 28, 2017
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Created: Jun 5, 2017
Updated: Jun 5, 2017
SVN Updated: Nov 28, 2017
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
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Other project properties
Category:DSP core
Language:VHDL
Development status:Stable
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a
License: Others
Language:VHDL
Development status:Stable
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a
License: Others
Description
This project comprises the VHDL description and configuration script of a configurable IIR filter.
The VIIRF can implement any transfer function (highpass, lowpass etc.) that can be represented as a cascade of second-order sections (SOS), which is an numerically very stable form of implementation.
The configuration script takes the (floating-point) SOS-matrix (and gain-matrix G, if required) and configures the (quantized) filter. It also simulates a step-response and generates testbench-files.
No vendor-specific language constructs (e.g., Block-RAM or DSP-cores) are used, such that the filter is usable in any development environment.
The sources and documentation are hosted at GitHub:
https://github.com/MauererMVIIRF
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