Alles, Matthias

Fehrenz, Markus

Viterbi Decoder (AXI4-Stream compliant)

HI, 


 I am gettine the fallowing Errors from my Isim Simulator. 

ISim P.20131013 (signature 0x7708f090)
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WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.


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This is a Full version of ISim.
Time resolution is 1 ps
Simulator is doing circuit initialization process.
at 0 ps, Instance /tb_dec_viterbi/inst_dec_viterbi/inst_ram_ctrl/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 0 ps, Instance /tb_dec_viterbi/inst_dec_viterbi/inst_ram_ctrl/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 0 ps, Instance /tb_dec_viterbi/inst_dec_viterbi/inst_ram_ctrl/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 0 ps, Instance /tb_dec_viterbi/inst_dec_viterbi/inst_ram_ctrl/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 0 ps, Instance /tb_dec_viterbi/inst_dec_viterbi/\gen_inst_reorder(1)\/inst_reorder/ : Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
at 0 ps, Instance /tb_dec_viterbi/inst_dec_viterbi/\gen_inst_reorder(0)\/inst_reorder/ : Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
Finished circuit initialization process.
at 5 ns, Instance /tb_dec_viterbi/inst_dec_viterbi/inst_ram_ctrl/\gen_generic_sp_ram(0)\/inst_generic_sp_ram/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
at 5 ns, Instance /tb_dec_viterbi/inst_dec_viterbi/inst_ram_ctrl/\gen_generic_sp_ram(0)\/inst_generic_sp_ram/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
at 5 ns, Instance /tb_dec_viterbi/inst_dec_viterbi/inst_ram_ctrl/\gen_generic_sp_ram(1)\/inst_generic_sp_ram/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
at 5 ns, Instance /tb_dec_viterbi/inst_dec_viterbi/inst_ram_ctrl/\gen_generic_sp_ram(2)\/inst_generic_sp_ram/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
at 5 ns, Instance /tb_dec_viterbi/inst_dec_viterbi/inst_ram_ctrl/\gen_generic_sp_ram(3)\/inst_generic_sp_ram/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
Reading C:\Users\gontu\Desktop\test\WiFi_121_91/llr_BL_200_WL_55_AL_50_in.txt.
at 35 ns, Instance /tb_dec_viterbi/inst_dec_viterbi/inst_ram_ctrl/\gen_generic_sp_ram(0)\/inst_generic_sp_ram/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
at 35 ns, Instance /tb_dec_viterbi/inst_dec_viterbi/inst_ram_ctrl/\gen_generic_sp_ram(1)\/inst_generic_sp_ram/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
at 35 ns, Instance /tb_dec_viterbi/inst_dec_viterbi/inst_ram_ctrl/\gen_generic_sp_ram(2)\/inst_generic_sp_ram/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
at 35 ns, Instance /tb_dec_viterbi/inst_dec_viterbi/inst_ram_ctrl/\gen_generic_sp_ram(3)\/inst_generic_sp_ram/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
at 45 ns, Instance /tb_dec_viterbi/inst_dec_viterbi/inst_ram_ctrl/\gen_generic_sp_ram(0)\/inst_generic_sp_ram/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
at 45 ns, Instance /tb_dec_viterbi/inst_dec_viterbi/inst_ram_ctrl/\gen_generic_sp_ram(1)\/inst_generic_sp_ram/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
at 45 ns, Instance /tb_dec_viterbi/inst_dec_viterbi/inst_ram_ctrl/\gen_generic_sp_ram(2)\/inst_generic_sp_ram/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
at 45 ns, Instance /tb_dec_viterbi/inst_dec_viterbi/inst_ram_ctrl/\gen_generic_sp_ram(3)\/inst_generic_sp_ram/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
at 55 ns, Instance /tb_dec_viterbi/inst_dec_viterbi/inst_ram_ctrl/\gen_generic_sp_ram(1)\/inst_generic_sp_ram/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
at 55 ns, Instance /tb_dec_viterbi/inst_dec_viterbi/inst_ram_ctrl/\gen_generic_sp_ram(2)\/inst_generic_sp_ram/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
at 55 ns, Instance /tb_dec_viterbi/inst_dec_viterbi/inst_ram_ctrl/\gen_generic_sp_ram(3)\/inst_generic_sp_ram/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.

I am not getting any Output data from the Decoder. The s_axis_output_tdata Signal is always Zero because of the above error's. so Decoder is interpreting all the values into 0 for all the similation time. I have added the new package. so there is no compilation error just Simulation Errors.

Simulation Error

The testbench provides blocks of data to the Viterbi decoder, however if the input block is divided into two seperate blocks, there will be an error at the divided place.

data  <=1=><=2=><=3=><=4=>-----<=5=><=6=><=7=><=8=>
valid -------------------|_____|-------------------
last  _______________________________________|----|
error ______________|----|_________________________

core doesnt work when input block is divided

I am using the core for DVB-s configuration, I am setting the 

window length 69
acq length    64

but it doesn't give output.

Working fine for
 
window length 66
acq length    61

or lower

window length

The testbench provides blocks of data to the Viterbi decoder with the s_axis_input_tvalid line asserted for the entirety of the block. In other words, the throughput into the decoder is 1 bit (2 symbols)/clock.

If the testbench is modified to provide blocks of data to the Viterbi decoder such that the s_axis_input_tvalid line is only periodically asserted, the decoder does not function and outputs more bits than were input into the decoder. In other words, if the throughput into the decoder is less than 1 bit (2 symbols)/clock, the decoder fails.

Thanks for putting this core together, by the way!

Core doesn't work with tvalid not kept constantly low

Hi

I am trying to simulate the viterbi decoder core you provided 
using the ISE simulator. But It gives an error "pkg_trellis is not compiled ".
Also the package "pkg_trellis" fails in behavourial check syntax.

compilation error

Modelsim 10.0a does not allow a function to be called before it is elaborated, so pkg_param_derived.vhd and pkg_trellis.vhd fail to compile. One solution is to change the following constants to deferred constants:

In pkg_param_derived.vhd:

ENCODER_MEMORY_DEPTH
NUMBER_TRELLIS_STATES
BW_TRELLIS_STATES
BW_MAX_WINDOW_LENGTH
BW_BRANCH_RESULT
BW_MAX_PROBABILITY

In pkg_trellis.vhd:

PREVIOUS_STATES
TRANSITIONS
INITIALIZE_TRELLIS

For example, the line in the package should not define the value:

    constant PREVIOUS_STATES    : t_previous_states;

The value should be specified in the package body (after the necessary function)

    constant PREVIOUS_STATES    : t_previous_states := calc_previous_states;

compilation errors in modelsim 10.0a

In perform_simulation.sh, the compilation of pkg_types.vhd needs to occur before pkg_components.vhd, or else the compilation fails when running the script from an empty directory.

compilation order is incorrect in perform_simulation.sh

Hi
I recently designed A Turbo decoder for DVB but It really consumes lots of memory. How Can I reduce memory need. Is there another method for simplifying the operations except Max log method.

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Viterbi Decoder (AXI4-Stream compliant)