OpenCores

WISHBONE Conmax IP Core :: Overview



Project maintainers

Details

Name: wb_conmax
Created: Oct 23, 2001
Updated: Feb 10, 2004
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star0you like it: star it!

Other project properties

Category:System on Chip
Language:Verilog
Development status:Stable
Additional info:
WishBone compliant: No
WishBone version: n/a
License:

Description

This is a WISHBONE Interconnect Matrix IP core.It can interconnect up to 8 Masters and 16 Slaves

Some of the main features are:
- Up to 8 Masters
- Up to 16 Slaves
- 1, 2 or 4 priority levels
- Fully configurable

IMAGE: conmax.jpg

FILE: conmax.jpg DESCRIPTION: Example SoC with the CONMAX IP Core

Status

- October 2002, Maintenance update: Fixed a typo in parameter passing and in the specification
- May 2002. Several users of the core have reported that the core performs as specified. Project is now considered completed.
- 10/19/2001 Initial Release.
- I will post a message to cores@opencores.org each time I have an update

Change log

- 10/19/2001 Initial Reslease

<br><br><font size=-1>This IP Core is provided by:</font>

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