Generic FIFO
Project maintainers
Details
Name: wb_fifo
Created: Jun 8, 2014
Updated: Jan 22, 2022
SVN Updated: May 12, 2015
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Created: Jun 8, 2014
Updated: Jan 22, 2022
SVN Updated: May 12, 2015
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star8you like it: star it!
Other project properties
Category:Memory core
Language:VHDL
Development status:Beta
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Language:VHDL
Development status:Beta
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
A very generic implementation of a FIFO. Makes good use of VHDL transactors for data transfers. Does not support Wishbone yet, but it's planned.
A newer version using a dual-port, dual-clock RAM and built-in clock domain synchronizers is available. Please email me at daniel.kho@logik.haus to enquire about this IP.
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