M. Harte, Howard

Wishbone LPC Host and Peripheral Bridge

The stop frame should be two clocks for quiet mode and three for continuous mode.  Currently, it is the other way around.

Serirq: incorrect stop frame

the LPC peripheral core inserts at least one wait-state following a firmware memory write.  According to the LPC specification, firmware writes must not insert any wait-states, and immediately respond with READY.

LPC firmware writes must not insert wait-states.

propagate wishbone errors on peripheral core WBM to host core WBS.

propagate Wishbone errors across LPC interface

The LPC peripheral core reports READY for the SYNC phase of multi-byte DMA transfers, when it should report READY+MORE for all bytes except the final byte.

LPC DMA does not report READY+MORE for multi-byte transfers

the multi-byte firmware accesses incorrectly follow the multi-byte DMA algorithm and issue a SYNC sequence between each byte transferred.  Instead, multi-byte firmware accesses should issue a single SYNC sequence following the transfer of the multi-byte data phase.

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Wishbone LPC Host and Peripheral Bridge