OpenCores

Wishbone LPC Host and Peripheral Bridge

wishbone byte strobe handling Bug

#13 opened almost 13 years by adyer

host SYNC error handling Bug

#12 opened almost 13 years by adyer

LPC_ST_P_TAR2 and LPC_ST_WB_RETIRE have same value Bug

#11 opened almost 13 years by adyer

The LPC peripheral should never drive the BUS during LPC_ST_H_TAR2 state Bug

#10 opened about 15 years by jbouchat

The LPC peripheral doesn't handle "abort" command Bug

#9 opened about 15 years by jbouchat

Quartus v8.1 synthesis problem Bug

#8 opened over 15 years by tcdev

Serirq: incorrect stop frame Bug

#7 opened almost 16 years by hharte

LPC Peripheral illegaly drives the bus during TAR Bug

#6 opened over 16 years by danielpreda

LPC Host does not end a DMA WORD cycle upon Ready response Bug

#5 opened over 16 years by danielpreda

LPC firmware writes must not insert wait-states. Bug

#4 opened over 16 years by hharte

propagate Wishbone errors across LPC interface Idea

#3 opened over 16 years by hharte

LPC DMA does not report READY+MORE for multi-byte transfers Bug

#2 opened over 16 years by hharte

Spec violation for multi-byte firmware accesses Bug

#1 opened over 16 years by hharte

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