While the greatest percentage of the logic for this processor has been verified, there are still a copule of areas of concern.
1) Interrupt testing should be better
2) hazard testing should be better.
3) There is at present not a written verification plan.
Guy Hutchison (see TV80 project) has synthesized an early version of the core in a 130nm TSMC process. He determined the design to contain about 20k gates and run at about 240 Mhz. While the speed is somewhat less than "target", optomizations of the logic should increase this somewhat.
I have synthesized the present version in Altera tools. (Stratus II) Initial resuts indicate 90 Mhz operation. I hope to be able to improve that significantly with some
work on the decoding logic.
This machine executes a byte instruction on each clock tick.
I have noticed a significant number of downloads of the code. I do not consider present level of verification sufficient to risk use in an expensive ASIC. I would like to run a well considered (and well written) "hazards" test. If anyone is interested enough in the core to volunteer help with this area please let me know.
10/2/2007 bugs reported by Stephen Warren and Howard Harte have been fixed and the data base has been updated. We are working on a better hazard test and a complete verification plan.
Design document complete and in CVS
RTL complete and built
initial verification phase (complete instruction test) PASSED
The purpose of the Wishbone Z80 development is to provide a “low-end engine” (written in verilog) that could logically interface with many of the low-end verilog peripherals available to the community, while providing sufficient “horsepower” to be used effectively with the more interesting “high end” peripherals.
The deign is conceived to operate efficiently with internal static RAM. Thus, a two stage pipeline is implemented to allow instruction execution at the access rate of a 32 kbyte RAM. (This could be well over 300 Mhz. depending on implementation technology.)