OpenCores

DragonBall/68K Wishbone interface

Project maintainers

Details

Name: wbif_68k
Created: Dec 2, 2002
Updated: Feb 14, 2004
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star0you like it: star it!

Other project properties

Category:Other
Language:Verilog
Development status:Stable
Additional info:Design done, FPGA proven
WishBone compliant: Yes
WishBone version: n/a
License:

Description

This is a Motorola DragonBall/68K to Wishbone bridge. The core translates the 16bit DragonBall/68K bus into a full featured 16bit Wishbone master bus.

Features

- 16bit Motorola DragonBall/68K Interface
- 16bit full featured RevB.3 Wishbone Classic Master interface
- programmable address-bus size
- static synchronous design
- fully synthesisable
- 6LUTs in a Spartan-II, 32LCELLs in an ACEX

Status

Design is finished and available in Verilog for download from OpenCores CVS.