Created: Oct 4, 2018
Updated: Oct 5, 2018
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WishBone compliant: No
WishBone version: n/a
This is an experimental oscilloscope VHDL design working on the Xilinx Spartan-3E starter board.
The analog signal is sampled with a TI ADC08200 converter currently at 160MSPS (max. feasible fs in this setup is TBD).
The output is displayed on a 12" Samsung LCD (LTN121W1-L03) of an old laptop with 1280x800 pixels, the interface is FPD-link (3+1 channels LVDS) operating at 280MHz (=7*pixel_frequency).
The user interface controller is a PS2 mouse: positioning, buttons and scroll wheel.
Both the FPGA and the LCD are >10 years old, but the design could be ported to a newer platform operating at higher frequency.
Current features and limitations:
- 2 channels (only 1 channel was tested until now)
- Time base from 500ns/div, that is 1 pixel/sample at 160MSPS and 80pixels/div (interpolation is not applied)
- RUN/STOP modes (Single measurement is to be implemented)
- Trigger modes: rising or falling edge; auto or normal; trigger level and delay positioning in the waveform window with the mouse
- Acquisition modes: normal or peak detect. (averaging is to be implemented)
- Display modes: X-t, roll. (X-Y is to be implemented)
- Waveform cursor is not implemented yet
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