This is a Verilog implementation of the XTEA block cipher. It works on two 32-bit blocks of data at a time with a 128-bit key. A proper OpenCores specification for this unit will be written at some point. Wishbone compliance is also on the TODO list. This implementation was adapted from the public domain C release of the algorithm from David Wheeler and Roger Needham by David Johnson. It is licensed under the GNU Lesser General Public License.
- a very small, efficient implementation
- what more do you need?
The current stable release is version 1.0. This release has seperate encipher/decipher units. A test-bench is available and included in the download. Version 1.0 is not licensed under the LGPL - it is public domain. Each unit accepts data in data_in1 and data_in2 and a key in key_in. The all_done wire is raised when the results of the operation are ready to be read from data_out1 and data_out2. They need to be reset before each use. This release has been FPGA-proven on an Altera Stratix EPS1S10F672C6-ES running at 25.175MHz. Higher clock speeds have not been tested. Please report back if you get the design up-and-running (especially if you get it running as an ASIC) or if you have it running at a higher clock speed. Note: the download page doesn't appear to be working at the moment, but you can grab the release from CVS.
Originally the project was split into seperate encipher/decipher units, but these have now been combined into a single unit. The test-bench has not yet been updated for the new combined unit. The unit accepts data in data_in1 and data_in2, a key in key_in and the mode in mode (1 for encipher, 0 for decipher). The all_done wire is raised when the results of the operation are ready to be read from data_out1 and data_out2. It needs to be reset before each use. This combined unit, as of yet, has not been tested.