 Integer Square Root

1 bit adpcm codec

2D FHT

4-bit system

5x4Gbps CRC generator designed with standard cells

8 bit Vedic Multiplier

8-bit Brent-Kung Adder

8-bit Kogge Stone Adder

Adder library

AES128

Anti-Logarithm (square-root), base-2, single-cycle

BCD adder

Binary to BCD conversions, with LED display driver

Bluespec SystemVerilog Reed Solomon Decoder

Booth Array Multiplier

cavlc decoder

Cellular Automata PRNG

CF Cordic

CF FFT

CF Floating Point Multiplier

Complex Arithmetic Operations

Complex Gaussian Pseudo-random Number Generator

Complex Multiplier

Complex Operations ISE for NIOS II

Configurable AES-GCM 128-192-256 bits

configurable cordic core in verilog

configurable CRC core

Configurable Parallel Scrambler

CORDIC arctangent for IQ signals

CORDIC core

CRCAHB

cr_div - Cached Reciprocal Divider

DCT - Discrete Cosine Transformer

Discrete Cosine Transform core

double_fpu_verilog

DVB-S2 LDPC Decoder

Elliptic Curve Group

Fixed Point Arithmetic Modules

Fixed Point Math Library for Verilog

Fixed Point Square Root (Recursive Algorithm)

Fixed-point quadratic polynomial

Floating Point Adder and Multiplier

Floating-Point Logarithm Unit 

floating_point_unit

FPGA-based Median Filter

FPU Double VHDL

FT816Float - Floating point accelerator

Gaussian Noise Generator

Generic Booth Multiplier

Generic Galois LFSR

Generic LFSR Generator

Generic Parameterized Carry Look ahead adder

GNExtrapolator

Hardware Division Units

Hardware implementation of Binary Fully Digital Phase Locked Loop

Hardware Load Balancer for Multi-Stage Software Router

HCSA adder and Generic ALU based on HCSA

Heap sorter for FPGA

Hello Digital World Counter

HIERARCHICAL Integer Multiplier unit

Huffman Decoder

LCD162B Behavior Model

LFSR-Random number generator

Logarithm function, base-2, single-cycle

LZRW1 Compressor Core

Matrix multiplication and inversion

Maximum/Minimum binary tree finder

Memory Polynomial Model for Digital Predistortion

MESI Coherency InterSection Controller

miniled_local_dimming_algorithm

mod3_calc

MODBUS Implementation in VHDL

Model of hybrid classical-quantum computing method

Multiplier library

Multiply-Accumulate Operation (MAC)

Non Linear Pseudo Random Generator

Numbert sort device O(N)

openFPU64

Parameterizable adder tree

Parameterizable integer square root by the digit-by-digit method

Parametrized FFT engine

PID Controler

pipeline mips in vhdl

Population Counter Generator 

Priority Encoder

PYRAMID Integer Multiplier unit

QuadFixedPoint32 Arithmetic Unit

radix 4 complex fft

Radix-4 Reciprocal  Square Root, Division and Square Root IP Core 

Ray Tracing Arithmetic Engine

Reconfigurable Hardware Platform

Reed-Solomon Decoder 

Requantizer

Signed / unsigned multiplier and divider with prime number generator as test circuit

Signed integer divider

SineAndCosineTable

Single 14 Segment Display Driver with Limited ASCII Decoder 

Single Clock Unsigned Division Algorithm

Project	Files	Statistics	Status	License	Wishbone version
Ethernet MAC 10/100 Mbps		Stats		LGPL
I2C controller core		Stats		BSD	B.3
RXAUI Interface and XAUI to RXAUI Interface Adapter		Stats
SPI Master/Slave Interface		Stats		LGPL

Browse

Arithmetic core 2

Communication controller 4

Crypto core 1

ECC core 1

Library 1

Other 1

Processor 9

System on Chip 1

Testing / Verification 2

Video controller 2