RXAUI Interface and XAUI to RXAUI Interface Adapter
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Details
Name: rxaui_interface_and_xaui_to_rxaui_interface_adapter
Created: Mar 31, 2009
Updated: Oct 22, 2009
SVN Updated: Apr 2, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 0 solved
Created: Mar 31, 2009
Updated: Oct 22, 2009
SVN Updated: Apr 2, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 0 solved
Star1you like it: star it!
Other project properties
Category:Communication controller
Language:Verilog
Development status:Mature
Additional info:ASIC proven, Design done, FPGA proven, Specification done
WishBone compliant: No
WishBone version: n/a
License:
Language:Verilog
Development status:Mature
Additional info:ASIC proven, Design done, FPGA proven, Specification done
WishBone compliant: No
WishBone version: n/a
License:
Overview
RXAUI interface uses two 6.25Gbps SERDES lanes to carry 10GE, instead of using four 3.125Gbps SERDES lanes.
This enables a high port count lower power multi 10GE SOCs.
This projects provides the specifications of RXAUI interface and the verilog code for an adapter from
a XAUI to RXAUI interface
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