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Written in:
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VHDL
Verilog & VHDL
Verilog
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Stage:
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Alpha
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License:
Any license
GPL
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CERN-OHL-S
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Wishbone version:
Any version
B.3
B.4
ASIC proven
Design done
FPGA proven
Specification done
OpenCores Certified
Arithmetic core
119
Prototype board
42
Communication controller
219
Coprocessor
10
Crypto core
81
DSP core
49
ECC core
24
Project
Files
Statistics
Status
License
Wishbone version
802.3an LDPC Decoder
Stats
802.3an LDPC Encoder
Stats
CF LDPC Decoder
Stats
Configurable BCH Encoder and Decoder
Stats
LGPL
Configurable Hamming Generator
Stats
GPL
Constellation Encoder
Stats
Double error correcting (DEC) BCH encoder / decoder
Stats
LGPL
ham_7_4_enc
Stats
PCI Express 16 bit CRC verilog file
Stats
Product Code Iterative Decoder
Stats
BSD
Reed Solomon (9,5) Encoder/Decoder
Stats
LGPL
Reed Solomon Codec
Stats
Others
Reed Solomon Decoder (204,188)
Stats
GPL
Reed Solomon Encoder
Stats
Reed Solomon Encoder/Decoder
Stats
LGPL
Reed-Solomon Codec Generator
Stats
LGPL
Reed-Solomon Decoder (31, 19, 6)
Stats
Reed-Solomon Decoder/Encoder
Stats
LGPL
RS_5_3_GF256
Stats
Spread Spectrum modulator and demodulator using BPSK
Stats
LGPL
Turbo Decoder
Stats
LGPL
Ultimate CRC
Stats
GPL
Viterbi Decoder (AXI4-Stream compliant)
Stats
GPL
Yet Another Hamming Encoder and Decoder
Stats
LGPL
Library
21
Memory core
51
Other
120
Processor
227
System on Chip
86
System on Module
2
System controller
21
Testing / Verification
37
Video controller
50
Uncategorized
94
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