Written in:Any languageVHDLVerilog & VHDLVerilogSystemCBluespecC/C++Other

Stage:Any stagePlanningMatureAlphaBetaStable

License:Any licenseGPLLGPLBSDCERN-OHL-SCERN-OHL-LCERN-OHL2-POthers

Wishbone version:Any versionB.3B.4

ASIC proven

Design done

FPGA proven

Specification done

OpenCores Certified

Arithmetic core 119

Prototype board 42

Communication controller 218

Coprocessor 10

Crypto core 81

DSP core 49

ECC core 24

Library 21

Memory core 51

Other 119

Processor 227

System on Chip 86

System on Module 2

System controller 21

Project	Files	Statistics	Status	License	Wishbone version
AC 97 Controller IP Core		Stats
AHBmaster for FPGA of microsemi		Stats		LGPL
External parallel port to internal wishbone master interface		Stats		GPL
Memory Controller IP Core		Stats
OCIDEC (OpenCores IDE Controller)		Stats
PCI bridge		Stats
PCI Express x1 16bit VERA testbench		Stats
PCI slave to WB master		Stats		LGPL
PCI Target		Stats		LGPL
PCIe SG DMA controller		Stats		LGPL
PCIe_DS_DMA		Stats		LGPL
PCIe_mini (PCI-Express to Wishbone Bridge for Xilinx FPGAs)		Stats		LGPL
PCIe_mini_axi4s_wb		Stats		LGPL
pci_mini		Stats		LGPL
Power Supply Sequencer		Stats		BSD
Programmable Interrupt Controller		Stats		LGPL
RS232 system controller		Stats		LGPL
scsi_chip		Stats
Synchronous-DRAM Controller		Stats
TI DSP and Xilinx FPGA Dev Board		Stats
WB LCD Character Display Controller		Stats		LGPL

Testing / Verification 37

Video controller 50

Uncategorized 94