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Details

Name: pci
Created: Sep 25, 2001
Updated: Jul 4, 2006
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 10 reported / 0 solved
Star3you like it: star it!

Other project properties

Category:System controller
Language:Verilog
Development status:Stable
Additional info:
WishBone compliant: Yes
WishBone version: n/a
License:

Current Status / News

Current Status / News changed on the 7th of May, 2003. - WebPack 5.2 project file with constraints for VGA Test Application (pci crt) was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) - CVS link - PCI Bridge COMPLETE & TESTED. We are waiting for FEED-BACK! - TESTBENCH for 32-bit PCI bridge (PCI IP Core) is done. - PCI IP Core Design document is done (rev. 0.1). - PCI IP Core Specification is updated (rer. 0.6). - Sample application, bit-stream for Insight's PCI development kit, also available. - Design synthesized and tested in a FPGA with Insight's PCI development kit (Spartan II 150k gates, speed grade -5). Demo is a VGA Test Application. See Test Application page and its subpages. - RTL design for 32-bit PCI bridge (PCI IP Core) is done.

Description

The PCI IP core (PCI bridge) is a member of a family of open source cores. It is a bus bridge device between the WISHBONE SoC bus and the PCI local bus. Both sides of bridge can operate at totally independent clock frequencies. It consists of two independent units, one handling transactions originating on the PCI bus, the other one handling transactions originating on the WISHBONE bus. Performance features include 32-bit bus interfaces on both sides, high level of performance and flexibility like burst data transfers, memory access optimizing command usage etc. The code is completely GENERIC (except for RAM primitives), which makes the core easily retargetable for any FPGA or ASIC technology.

Purpose of the PCI Bridge project

FIRST: All commercial PCI soft cores, that we noticed, are PCI interfaces. They have different backend interfaces. A system designer using PCI interface for some application must also be aware of the PCI protocol. With a PCI bridge a designer considers only the system bus (WISHBONE SoC bus) and can easily focus on his application. (It is true, that PCI interfaces occupy less space, but they do not incorporate a back-end) SECOND: The same code for FPGA prototypes and ASIC end-products. The code is completely GENERIC, which makes it retargetable for any FPGA or ASIC technology. THIRD: We believe that the PCI bridge will be better tested and more improved because it is an open source PCI bridge core. Any help testing will be appreciated. Go to PCI Forum or contact mihad@opencores.org and tadej@opencores.org.

Documentation

The core has been designed to offer as much flexibility as possible to all kinds of applications. You can download the latest documents on the download page or from the following links: - PCI Bridge Datasheet, - PCI Bridge Databook, - PCI Bridge Specification (describes the PCI IP Core operation and it's registers), - PCI Bridge Design document (describes the PCI IP Core structure, PCI Testbench with testcases and all defines).

Testbench

The PCI bridge Testbench was designed to test most of possibilities: - All tests run several times with all combinations of typical Initial and Subsequent wait states - Configuration operation of HOST bridge; finding devices, interrupt acknowledge cycle, etc. - Configuring GUEST bridge - Many combinations of WB to PCI single and burst transactions with various terminations on WB and on PCI bus and with address translation enabled/disabled - Many combinations of PCI to WB single and burst transactions with various terminations on WB and on PCI bus and with address translation enabled/disabled - Many combinations of error and interrupt handling with reporting of errors and interrupts enabled/disabled - Fast Back-to-Back testing (PCI Target is capable of Fast Back-to-Back responding from different PCI masters) - Many combinations of transaction ordering For better tested design, we prepared a script for running a simulator with defines set by an user or 13 times (we use Cadence NCsim) with different combinations of defines (HOST/GUEST, different clocks, different number of images, etc.). The last test has defines set by the user. There are also LOG files created from all compiling and from testbench. The main testbench LOG file is pci_tb.log, which marks all testcases as SUCCESSFUL or FAILED. Other LOG files are from PCI and WB monitors. All are included in the PCI project and are downloaded together from download page or are available separately from PCI CVS. The PCI bridge Testbench is described in the PCI Bridge Design document and can be downloaded from the download page or from the link at the Documentation chapter.

PCI Bridge Features

The list of the main features of the PCI bridge IP core:
- 32-bit PCI interface
- Fully PCI 2.2 compliant (with 66 MHz PCI specification)
- Separated initiator and target functional blocks
- Supported initiator commands and functions:
- Memory Read, Memory Write
- Memory Read Multiple (MRM)
- Memory Read Line (MRL)
- I/O Read, I/O Write
- Configuration Read, Configuration Write
- Bus Parking
- Interrupt Acknowledge
- Host Bridging
- Supported target commands and functions:
- Type 0 Configuration Space Header
- (Type 0 is used to configure agents on the same bus segment)
- (Type 1 is used to configure across PCI-to-PCI bridges)
- Parity Generation (PAR), Parity Error Detection (PERR# and SERR#)
- Memory Read, Memory Write
- Memory Read Multiple (MRM)
- Memory Read Line (MRL)
- Memory Write and Invalidate (MWI)
- I/O Read, I/O Write
- Configuration Read, Configuration Write
- Target Abort, Target Retry, Target Disconnect
- Fast Back-to-Back Capable response
- Full Command/Status registers
- WISHBONE SoC Interconnection Rev. B compliant interface on processor side (master with Target PCI and slave with Initiator PCI interface)
- Configurable on-chip FIFOs

The following picture shows the PCI bridge architecure which is implemented as a Host PCI bridge.

IMAGE: PCI_HOST_architecture.jpg

FILE: PCI_HOST_architecture.jpg
DESCRIPTION: Host PCI Bridge Architecture

Utilization

We made a synthesis for FPGA and for ASIC. For ASIC we synthesised just a PCI Bridge, while for FPGA we implemented a whole Test Application (PCI Bridge and CRT cores).

Technology FPGA size Silicon Area Speed Power Consumption
FPGA Xilinx Spartan II -5 * 1300 slices / * 33MHz PCI, 42MHz WB TBD
ASIC .18u VS library / * 1.0965 mm2 66MHz PCI, 200MHz WB TBD

  • FPGA synthesis includes two cores: PCI Bridge and CRT. 42 MHz WISHBONE speed in FPGA is with CRT core. PCI Bridge has approximately 1300 slices and 3 Block SelectRAM+ memories, while CRT has approximately 100 slices and 2 Block SelectRAM+ memories. Here you can see the synthesis LOG file. PCI Bridge was synthesised with following characteristics:
    - GUEST bridge with PCI to Configuration space IMAGE (16MB min), 1 PCI to WB IMAGE (16MB min) and 1 WB to PCI IMAGE (2GB min)
    - 64 words (32-bit) of WB Read FIFO and 8 words (32-bit) of WB Write FIFO (3 Block SelectRAM+ memories)
    - 16 words (32-bit) of PCI Read and Write FIFO (Distributed Block SelectRAM)
    - Address translation was not implemented
  • ASIC synthesis includes just PCI Bridge. Silicone Area is 1.0965 mm2 and includes 2KB of dual-port memory for 4 FIFOs (approximately half of the area). PCI Bridge was synthesised with following characteristics:
    - GUEST bridge with PCI to Configuration space IMAGE (1MB min), 1 PCI to WB IMAGE (1MB min) and 1 WB to PCI IMAGE (1MB min)
    - 127 words (32-bit) of memory for each one of 4 FIFOs; WB Read, WB Write, PCI Read and PCI Write FIFO
    - Address translation was not implemented