mihad

Markovic, Tadej

PCI bridge

In using the PCI bridge I would also like to give it proper attribution, but the license wasn't clear to me.

Would it be possible to fix the license pick on the project page, and possibly add licensing headers to the project files?

Best regards // Andreas

PCI bridge license

The constant PCI_MBIST_CTRL_WIDTH is not defined

Instantiations are present in the following files.

$ grep -nrw "art_hsdp_64x40_bist" . --include=\*.v
./pci_wb_tpram.v:219:        art_hsdp_64x40_bist /*#(dw, 1<<aw, aw) */ artisan_sdp
./pci_pci_tpram.v:123:        art_hsdp_64x40_bist /*#(dw, 1<<aw, aw) */ artisan_sdp

Failed to locate the module declaration for: art_hsdp_64x40_bist

The missing module is instantiated in the following locations

	$ grep -nrw "vs_hdtp_64x40_bist" . --include=\*.v
	./pci_wb_tpram.v:170:        vs_hdtp_64x40_bist i_vs_hdtp_64x40_bist
	./pci_pci_tpram.v:170:        vs_hdtp_64x40_bist i_vs_hdtp_64x40_bist

Failed to locate the module declaration for: vs_hdtp_64x40_bist

Hi,
I am not able to locate the module "RAM16X1D". It is port-mapped in the file ./trunk/rtl/verilog/pci_ram_16x40d.v as follows.

	./trunk/rtl/verilog/pci_ram_16x40d.v:95:    RAM16X1D ram39 (.DPO(data_out[39]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[39]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));

RAM16X1D module not found

Can you generate a VHDL version for your PCI bridge. Some tools can do that automatically but the result is not really good.

VHDL version for PCI Bridge

It would be nice if the PCI bridge project page specified if DMA transfers were possible on the PCI bus.  There have been innumerable (mostly unanswered) questions on the list asking if this core supports PCI DMA.

Documentation of DMA support (or lack therof)

I want use the core to develop a E2/E3 card ,and it alse need a deep FIFO,someone can help me ?

a pci data gather card with E3/E2

DMA transfer can be  implemented for various data transfers between wishbone bus and pci bus. all the popular pci cores support this feature

DMA transfer for PCI bridge

There is supported only Linear Incrementing burst mode. Additional burst mode is Cacheline Wrap mode. Implementing this in FPGA is not so good, since it would make the design much larger. Now unsupported burst mode is broken into single transfers.

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PCI bridge