OpenCores

Public Profile of Rozhdestvenskiy, Dmitry

Info

Username	dmitryr
Fullname	Rozhdestvenskiy, Dmitry
Email	dmitryr@openco... (@opencores.org)
Country	Russian Federation

Projects 2

S1 Core 3
OpenSPARC-based SoC 3
Total 6 received

Submitted bugs 5

Open 5

Open SpaceWire Light — TX clock, DDR buffers

Open Ethernet MAC 10/100 Mbps — Irregular clock domain crossing

Open OpenSPARC-based SoC — T2 FPGA optimizations

Open OpenSPARC-based SoC — L2 cache

Open OpenSPARC-based SoC — FPGA RAMs

Closed 0

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