S1 Core

Project maintainers

Details

Name: s1_core
Created: Jan 3, 2007
Updated: Mar 11, 2018
SVN Updated: May 7, 2017
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 3 reported / 2 solved

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Other project properties

Category:Processor
Language:Verilog
Development status:Stable
Additional info:Design done
WishBone compliant: Yes
WishBone version: n/a
License: GPL

S1 Core briefly...

The S1 Core is a reduced version of the OpenSPARC T1 released by Sun Microsystems. While the T1 is a complete microprocessor with 8 cores (capable of running up to 32 concurrent threads) and includes a crossbar switch, L2 Caches and several other interfaces, the S1 takes only one 64-bit SPARC v9 core (capable of running from 1 up to 4 concurrent threads) and includes a Wishbone Master Interface to connect to the cores available on OpenCores.

In recent years the project has not been actively worked on, so users are strongly advised to use Princeton University's OpenPiton project instead: http://parallel.princeton.edu/openpiton/