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| HDL IP with priority encoder as component | 1 | 1814 |
"RE: HDL IP with priority encoder as component"
by robfinch Mar 30, 2018 |
| Looking for Vivado VHDL simple cpu core | 1 | 2034 |
"RE: Looking for Vivado VHDL simple cpu core"
by jolup Mar 29, 2018 |
| RGB to HSL | 0 | 1870 |
"RGB to HSL"
by akifakkaya Mar 27, 2018 |
| Is there a 16bit MIPS processor with Wishbone bus? | 4 | 2376 |
"RE: Is there a 16bit MIPS processor with Wishbone bus?"
by jardel Mar 23, 2018 |
| Hardware Assisted IEEE 1588 IP Core | 1 | 1913 |
"RE: Hardware Assisted IEEE 1588 IP Core"
by bilal2228 Mar 13, 2018 |
| Running UVM example in System Verilog | 7 | 10554 |
"RE: Running UVM example in System Verilog"
by peermohamed Mar 13, 2018 |
| Verilog code for noc based on voq(virtual output queue) | 1 | 1868 |
"RE: Verilog code for noc based on voq(virtual output queue)"
by AleksandarK Feb 8, 2018 |
| Verilog code for few components. | 0 | 1738 |
"Verilog code for few components."
by AleksandarK Feb 1, 2018 |
| SD slave core | 2 | 2280 |
"RE: SD slave core"
by eaglepeng Jan 8, 2018 |
| ip-xact files | 8 | 11113 |
"RE: ip-xact files"
by olof Jan 5, 2018 |
| Verilog code for DDR SDRAM Controller Core | 16 | 18203 |
"RE: Verilog code for DDR SDRAM Controller Core"
by aikijw Dec 27, 2017 |
| PIC18 soft IP | 1 | 1961 |
"RE: PIC18 soft IP"
by dgisselq Dec 25, 2017 |
| Compression IP(verilog code) | 0 | 1767 |
"Compression IP(verilog code)"
by fgh123 Dec 14, 2017 |
| CI(common Interface) | 0 | 1709 |
"CI(common Interface)"
by maheshbutala Dec 13, 2017 |
| I2C master/slave core | 3 | 2420 |
"RE: I2C master/slave core"
by aikijw Dec 7, 2017 |
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