Uart2BusTestBench is implemented using Universal Verification Methodology to perform the functional verification to the RTL design released by Moti Litochevski and Steve MULLER (check this link ).
The Main Features :
You can download The Architecture Specifications from here
Field | Description | Possible Choices |
Active Edge | The active clock edge at which, the data is changed on the UART buses |
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First Bit | Represent the sequence through which the byte is serialized |
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Data Mode | The data representation through the text commands |
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Number of stop bits | The number of stop bits sent after the latest bit of each byte |
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Number of bits | The number of bits through each field transfer |
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Parity Mode | The used parity type through each byte |
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Response Time | Represent the maximum allowable time through which dut should respond to the driven request. |
No Limitations |