[128bit] Pseudo Random Number Generator Using Linear-feedback Shift Registers
Project maintainers
Details
Name: 128prng
Created: Aug 23, 2018
Updated: Aug 24, 2018
SVN: No files checked in
Bugs: 0 reported / 0 solved
Created: Aug 23, 2018
Updated: Aug 24, 2018
SVN: No files checked in
Bugs: 0 reported / 0 solved
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Other project properties
Category:Arithmetic core
Language:VHDL
Development status:Alpha
Additional info:FPGA proven, Specification done
WishBone compliant: No
WishBone version: n/a
License: LGPL
Language:VHDL
Development status:Alpha
Additional info:FPGA proven, Specification done
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
This PRNG uses Fibonacci LFSRs with a estimated period of 3.40282366920938463463374607431768211455 × 10^38 clock cycles Expression: X^128 + X^126 + X^101 + X^99 + 1
Avaible at:
https://github.com/rodrigowue128bit-prng
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