A. LeFevre, Howard

a VHDL 8254 Timer

I've got problem with updating value of the counter through APB interface, when updating two bytes (RW bits in control word set to "11"). Only LSB was updated. I've tried to find what's wrong and I made a change that helped (I don't know how this may affect other features). Here is output of diff command on gh_counter_control.vhd file:

        signal fe_hdcl   : std_logic;
        signal ird_busy  : std_logic;
        signal clr_hclsw : std_logic;
-
+       signal iCSr      : std_logic;
 begin

+
+       process(clk_i, rst)
+       begin
+               if rst = '1' then
+                       iCSr <= '0';
+               elsif rising_edge(clk_i) then
+                       iCSr <= iCS;
+               end if;
+       end process;
+
 ----------------------------------------------------


@@ -208,7 +218,7 @@ u2 : gh_register_ce
                  '0';

        ld_msb <= '1' when ((dwr = '1') and (iA = "00") and (control(5 downto 4) = "10") and (iCS = '1')) else
-                 '1' when ((dwr = '1') and (iA = "00") and (control(5 downto 4) = "11") and (dwb = '1') and (iCS = '1')) else
+                 '1' when ((dwr = '1') and (iA = "00") and (control(5 downto 4) = "11") and (dwb = '1') and (iCSr = '1')) else
                  '0';

        rd_lsb <= '0' when (hclsw = '1') else

Problem with updating value of the counter

I saw syncronisation problems with async clocks: Slow timer input clock(clk) and fast wishbone clock (clk_i), generics set properly.

JKFF U3 in gh_counter_control.vhd has iout and iload on inputs J and K:
  iout is derived from clk
  iload is derived from clk_i (ld_msb,dwr )

U3 is clocked with slow clock "clk" and does not see short iload pulses (clk_i) and m0_outh is not cleared so that in Mode 0 the output is not set to 0 when starting a new count by writing lsb/msb. 

Below the fix. I don't know if it breaks other modes, but as m0_outh is exclusively for Mode 0 I do not assume so. The fix is not elegant because it still does not synchronize right, it just syncs to the faster clock. Setup/Hold Time issues are still possible.

--- gh_counter_control.vhd      2008-08-02 19:22:28.000000000 +0200
+++ ../../../../modelsim/src/gh_counter_control.vhd     2011-05-13 14:52:06.689707400 +0200
@@ -326,7 +326,7 @@
 
 U3 : gh_jkff 
        PORT MAP (
-               clk => clk,
+               clk => clk_i,
                rst => rst,
                j => iout,
                k => iload,


Regards
Tobias

syncronisation

Hello, 

1. Why there are two input lines: wb_stb_i, wb_cyc_i ? can I apply them both to CS from my address decoder?

2. I am following he waveform in the dpf file in order to work with Mode3 and try to read the data from the counters (direct read and even Readback) but don't get the valid data or the lines are constantly at 0. Can anyone post a full waveform to how do the above?

see my waveform here: http://yfrog.com/muwaveform8254j

Info: The input clock I used for the counters was 5 times slower (and in sync) than the system clock (wb_clk_i). 

3. What is the maximum frequency for the clock inputs?

Many thanks in advance!

Few questions about the design -

Hi Howard:

  I have a problem at readback command.

  When I set readback command and read only counter without status, like 0xD2.
  It will not response "ack".
  Is this a bug or you have a special consider??

Thanks,
Joe

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a VHDL 8254 Timer