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A VHDL CAN Protocol Controller

## Description

A (as far as I know) untested VHDL translation of the Verilog Can protocol Controller  
  
To Download, click at the "Downloads" button upper right part of this page  
  
This project is a translation Igor Mohor's Verilog [http://opencores.org](http://opencores.org)project,can,overview (CAN Protocol Controller)

## Features

The modules have "\_vhdl\_" added to their names, to ease compare simulation with Verilog version (for those with mixed a language simulator)

## Status

use at own risk - have no had time to test/simulate  
  
check the Philips SJA1000 data sheet and the [http://opencores.org](http://opencores.org)project,can,overview (Verilog project page) for more information


<h2 id="description">Description</h2>
<p>A (as far as I know) untested VHDL translation of the Verilog Can protocol Controller<br />
<br />
To Download, click at the "Downloads" button upper right part of this page<br />
<br />
This project is a translation Igor Mohor's Verilog <a href="http://opencores.org" target="_blank">http://opencores.org</a>project,can,overview (CAN Protocol Controller)</p>
<h2 id="features">Features</h2>
<p>The modules have "_vhdl_" added to their names, to ease compare simulation with Verilog version (for those with mixed a language simulator)</p>
<h2 id="status">Status</h2>
<p>use at own risk - have no had time to test/simulate<br />
<br />
check the Philips SJA1000 data sheet and the <a href="http://opencores.org" target="_blank">http://opencores.org</a>project,can,overview (Verilog project page) for more information</p>


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A VHDL CAN Protocol Controller

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