OpenCores

A VHDL CAN Protocol Controller

Project maintainers

Details

Name: a_vhdl_can_controller
Created: Aug 23, 2007
Updated: May 5, 2017
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 2 reported / 0 solved
Star5you like it: star it!

Other project properties

Category:Communication controller
Language:VHDL
Development status:Stable
Additional info:Design done
WishBone compliant: No
WishBone version: n/a
License:

Description

A (as far as I know) untested VHDL translation of the Verilog Can protocol Controller

To Download, click at the "Downloads" button upper right part of this page

This project is a translation Igor Mohor's Verilog http://opencores.orgproject,can,overview (CAN Protocol Controller)

Features

The modules have "_vhdl_" added to their names, to ease compare simulation with Verilog version (for those with mixed a language simulator)

Status

use at own risk - have no had time to test/simulate

check the Philips SJA1000 data sheet and the http://opencores.orgproject,can,overview (Verilog project page) for more information