AHB2WISHBONE
Project maintainers
Details
Name: ahb_m_wishbone_s
Created: Aug 31, 2020
Updated: Sep 2, 2020
SVN Updated: Sep 2, 2020
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Created: Aug 31, 2020
Updated: Sep 2, 2020
SVN Updated: Sep 2, 2020
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star0you like it: star it!
Other project properties
Category:System on Chip
Language:Verilog
Development status:Stable
Additional info:Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL
Language:Verilog
Development status:Stable
Additional info:Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL
This ip core provides a simple robust interface between AHB-LITE master & WISHBONE salve. Tested in an arm based SoC with the sdram controller 8/16/32 from openCores. FPGA proven with intel/altera cyclone 10.
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