Computer Operating Properly
Project maintainers
Details
Name: cop
Created: May 22, 2009
Updated: Jan 27, 2010
SVN Updated: Sep 17, 2011
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Created: May 22, 2009
Updated: Jan 27, 2010
SVN Updated: Sep 17, 2011
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star2you like it: star it!
Other project properties
Category:Other
Language:Verilog
Development status:Beta
Additional info:Design done, Specification done
WishBone compliant: Yes
WishBone version: n/a
License: BSD
Language:Verilog
Development status:Beta
Additional info:Design done, Specification done
WishBone compliant: Yes
WishBone version: n/a
License: BSD
Description
The Computer Operating Properly Module, COP, is a watchdog timer module that triggers a system reset if it is not regularly serviced by writing two specific words to its control registers. The intention of the module is to bring an embedded system back to a “good” state after the software program has lost control of the system.
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