MaSoCist Soc builder/simulator :: Overview

Project maintainers


Name: masocist
Created: Nov 29, 2018
Updated: Nov 30, 2018
SVN: No files checked in
Bugs: 1 reported / 0 solved
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Other project properties

Category:System on Chip
Development status:Mature
Additional info:Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: Others


The MaSoCist is an acronym for 'Martins SoC Instancing, Simulation Toolchain'.

It is a VHDL collection and toolchain based on various open source (and some proprietary) utilities to configure, build and maintain system on chip designs with the focus on lean and mean microcontrollers with optimum code density.

It features the following opensource CPU cores by default:
- neo430 (
- ZPU Zealot architecture
- ZPUng proprietary pipelined ZPU variant (VHDL edition only)

It includes a simple wishbone bridge for optional wishbone compliant core adaptation. All hardware definitions are maintained in XML source, which generates C headers, VHDL decoders and documentation in one 'go'.

Basic peripheral cores are included, such as SIC (system interrupt controller), UART, SPI, TIMER, etc.

The project is currently hosted at:

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