MaSoCist Soc builder/simulator

Description

The MaSoCist is an acronym for 'Martins SoC Instancing, Simulation Toolchain'.

It is a VHDL collection and toolchain based on various open source (and some proprietary) utilities to configure, build and maintain system on chip designs with the focus on lean and mean microcontrollers with optimum code density.

It features the following opensource CPU cores by default:

• neo430 CPU core from https://github.com/stnolting/neo430
• ZPU Zealot architecture
• ZPUng proprietary pipelined ZPU variant (VHDL edition only)

• RISC-V (rv32ui compatible) pyrv32 CPU (VHDL edition only)

It includes a simple wishbone bridge for optional wishbone compliant core adaptation. All hardware definitions are maintained in XML source, which generates C headers, VHDL decoders and documentation in one 'go'.

Basic peripheral cores are included, such as SIC (system interrupt controller), UART, SPI, TIMER, etc.

The project is currently hosted at:

https://github.com/hackfin/masocist