MC6803/6801 CPU
Project maintainers
Details
Name: mc6803
Created: Mar 31, 2019
Updated: May 15, 2019
SVN Updated: May 30, 2019
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 0 solved
Created: Mar 31, 2019
Updated: May 15, 2019
SVN Updated: May 30, 2019
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 0 solved
Star2you like it: star it!
Other project properties
Category:Processor
Language:Verilog
Development status:Stable
Additional info:Design done, FPGA proven, Specification done
WishBone compliant: No
WishBone version: n/a
License: LGPL
Language:Verilog
Development status:Stable
Additional info:Design done, FPGA proven, Specification done
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
This module is a 6803 CPU based on System68 and System01 by John E. Kent. I have translated the CPU core from VHDL to SystemVerilog and added some of the peripherals.
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