MCPU - A minimal CPU for a CPLD :: Overview

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    Name: mcpu
    Created: Jul 31, 2007
    Updated: Jan 20, 2014
    SVN Updated: Mar 10, 2009
    SVN: Browse
    Latest version: download (might take a bit to start...)
    Statistics: View
    Bugs: 1 reported / 1 solved
    Star0you like it: star it!

    Other project properties

    Development status:Stable
    Additional info:Design done, FPGA proven
    WishBone compliant: No
    WishBone version: n/a
    License: GPL

    MCPU - Minimal CPU for a 32 Macrocell CPLD

    MCPU is a minimal cpu aimed to fit into a 32 Macrocell CPLD - one of the smallest available programmable logic devices. While this CPU is not powerful enough for real world applications it has proven itself as a valuable educational tool. The source code is just a single page and easily understood. Both VHDL and Verilog versions are supplied. The package comes with assembler, emulator and extensive documentation.

    Please let me know if you find a good use for this CPU and put your project/publication/lecture notes on the web. I will try to maintain a list here. I know it already has found good use for many purposes.


    The CPU is accumulator based and supports a bare minimum of registers. The accumulator has a width of eight bits and is complemented by a carry flag. The program counter (PC) has a width of six bits which allows addressing of 64 eight bit words of memory. The memory is shared between program code and data.


    See Github for latest updates


    I moved the project archive over to Github for easier maintenance. You can find the latest version here: Github repository
    The opencore archive will stay a v1.06b

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