FORTH processor with Java compiler
Project maintainers
Details
Created: Oct 30, 2012
Updated: Oct 31, 2012
SVN Updated: Nov 24, 2012
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Other project properties
Language:VHDL
Development status:Stable
Additional info:Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
A 32-bit FORTH processor conforming to the DPANS'94. This processor was developed as diploma thesis to obtain the academic degree Diplomingenieur (Master of Computer Science) at Johannes Kepler University in Linz, Austria.
Details
- Pipelined (6-stage) instruction execution.
- 2 stacks instead of register array.
- memory common to data and instructions.
- optional 64-bit multiplier and divider.
- optional multicore possible
- ANSI 754 floating point arithmetic.
- Hardware is Little-Endian.
- an Interruptcontroller.
- an UART.
- board specific DDR2 memory controller
- a ROM containig the BIOS, sources included
- Vendor-independent code.
- A clean, modular design.
The projects are realized on Xilinx Spartan 3A Starter board, but can be moved to other Xilinx boards.
The following software is included:
A Java-client for communication between board and user. The client includes a FORTH-Assembler and a Java compiler. The sources are included.