Table of content

1. Introduction

The openMSP430 is a 16-bit microcontroller core compatible with TI's MSP430 family (note that the extended version of the architecture, the MSP430X, isn't supported by this IP). It is based on a Von Neumann architecture, with a single address space for instructions and data.

Depending on the selected configuration, this design can either be:
      •  FPGA friendly: the core doesn't contain any clock gate and has only a single clock domain. As a consequence, in this mode, the Basic Clock Module peripheral has a few limitations.

      •  ASIC friendly: the core contains up to all clock management options (clock muxes & low-power modes, fine grained clock gating, ...) and is also ready for scan insertion. In this mode, the Basic Clock Module offers all features listed in the official documentation.

It is to be noted that this IP doesn't contain the instruction and data memory blocks internally (these are technology dependent hard macros which are connected to the IP during chip integration). However the core is fully configurable in regard to the supported RAM and/or ROM sizes.

2. Core

2.1 Design structure

The following diagram shows the openMSP430 design structure:

CPU Structure
  • Frontend: This module performs the instruction Fetch and Decode tasks. It also contains the execution state machine.
  • Execution unit: Containing the ALU and the register file, this module executes the current decoded instruction according to the execution state.
  • Serial Debug Interface: Contains all the required logic for a Nexus class 3 debugging unit (without trace). Communication with the host is performed with a standard two-wire interface following either the UART 8N1 or I2C serial protocol.
  • Memory backbone: This block performs a simple arbitration between frontend, execution-unit, DMA and Serial-Debug interfaces for program, data and peripheral memory accesses.
  • Basic Clock Module: Generates MCLK, ACLK, SMCLK and manage the low power modes.
  • SFRs: The Special Function Registers block contain diverse configuration registers (NMI, Watchdog, ...).
  • Watchdog: Although it is a peripheral, the watchdog is directly included in the core because of its tight links with the NMI interrupts and PUC reset generation.
  • 16x16 Multiplier: The hardware multiplier peripheral is transparently supported by the GCC compiler and is therefore located in the core. It can be included or excluded at will through a Verilog define.

2.2 Limitations

The known core limitations are the following:
  • Instructions can't be executed from the data memory.

2.3 Configuration

It is possible to configure the openMSP430 core through the openMSP430_defines.v file located in the rtl directory (see file and directory description).
In this section, three sets of adjustabe user parameters are discussed in order to customize the core. A fourth set is available for ASIC specific options and will be discussed in the ASIC implementation section.

2.3.1 Basic System Configuration

The basic system can be adjusted with the following set of defines in order to match the target system requirements.

// Note: the sum of program, data and peripheral memory spaces must not
//      exceed 64 kB

// Program Memory Size:
//                     Uncomment the required memory size
//`define PMEM_SIZE_59_KB
//`define PMEM_SIZE_55_KB
//`define PMEM_SIZE_54_KB
//`define PMEM_SIZE_51_KB
//`define PMEM_SIZE_48_KB
//`define PMEM_SIZE_41_KB
//`define PMEM_SIZE_32_KB
//`define PMEM_SIZE_24_KB
//`define PMEM_SIZE_16_KB
//`define PMEM_SIZE_12_KB
//`define PMEM_SIZE_8_KB
//`define PMEM_SIZE_4_KB
`define PMEM_SIZE_2_KB
//`define PMEM_SIZE_1_KB

// Data Memory Size:
//                     Uncomment the required memory size
//`define DMEM_SIZE_32_KB
//`define DMEM_SIZE_24_KB
//`define DMEM_SIZE_16_KB
//`define DMEM_SIZE_10_KB
//`define DMEM_SIZE_8_KB
//`define DMEM_SIZE_5_KB
//`define DMEM_SIZE_4_KB
//`define DMEM_SIZE_2p5_KB
//`define DMEM_SIZE_2_KB
//`define DMEM_SIZE_1_KB
//`define DMEM_SIZE_512_B
//`define DMEM_SIZE_256_B
`define DMEM_SIZE_128_B

// Include/Exclude Hardware Multiplier

// Include/Exclude Serial Debug interface
`define DBG_EN

The only design considerations at this stage are:
  • Make sure that the program and data memories have the correct size :-P
  • The sum of program, data and peripheral memory space MUST NOT exceed 64 kB

Note: when selected, full custom memory sizes can be specified in the "Expert System Configuration" section.

2.3.2 Advanced System Configuration

In this section, some additional features are available in order to match the needs of more experienced users.


// Custom user version number
// This 5 bit field can be freely used in order to allow
// custom identification of the system through the debug
// interface.
// (see CPU_ID.USER_VERSION field in the documentation)
`define USER_VERSION 5'b00000

// Include/Exclude Watchdog timer
// When excluded, the following functionality will be
// lost:
//        - Watchog (both interval and watchdog modes)
//        - NMI interrupt edge selection
//        - Possibility to generate a software PUC reset
`define WATCHDOG

// Include/Exclude DMA interface support
//`define DMA_IF_EN

// Include/Exclude Non-Maskable-Interrupt support
`define NMI

// Number of available IRQs
// Indicates the number of interrupt vectors supported
// (16, 32 or 64).
`define IRQ_16
//`define IRQ_32
//`define IRQ_64

// Input synchronizers
// In some cases, the asynchronous input ports might
// already be synchronized externally.
// If an extensive CDC design review showed that this
// is really the case,  the individual synchronizers
// can be disabled with the following defines.
// Notes:
//        - all three signals are all sampled in the MCLK domain
//        - the dbg_en signal reset the debug interface
//         when 0. Therefore make sure it is glitch free.
`define SYNC_NMI
//`define SYNC_CPU_EN
//`define SYNC_DBG_EN

// Peripheral Memory Space:
// The original MSP430 architecture map the peripherals
// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
// The following defines allow you to expand this space
// up to 32 kB (i.e. from 0x0000 to 0x7fff).
// As a consequence, the data memory mapping will be
// shifted up and a custom linker script will therefore
// be required by the GCC compiler.
//`define PER_SIZE_32_KB
//`define PER_SIZE_16_KB
//`define PER_SIZE_8_KB
//`define PER_SIZE_4_KB
//`define PER_SIZE_2_KB
//`define PER_SIZE_1_KB
`define PER_SIZE_512_B

// Defines the debugger CPU_CTL.RST_BRK_EN reset value
// (CPU break on PUC reset)
// When defined, the CPU will automatically break after
// a PUC occurrence by default. This is typically useful
// when the program memory can only be initialized through
// the serial debug interface.
`define DBG_RST_BRK_EN

Design consideration at this stage are:
  • Setting a peripheral memory space to something else than 512B will shift the data memory mapping up, which in turn will require the use of a custom linker script. If you don't know what a linker script is and if you don't want to know what it is, you should probably not modify this section.
  • The sum of program, data and peripheral memory space MUST NOT exceed 64 kB

Note: when selected, full custom peripheral memory space can be specified in the "Expert System Configuration" section.

2.3.3 Expert System Configuration

In this section, you will find configuration options which are relevant for roughly 0.1% of the users (according to a highly reliable market analysis ;-) ).

// IMPORTANT NOTE:  Please update following configuration options ONLY if
//                 you have a good reason to do so... and if you know what
//                 you are doing :-P

// Select serial debug interface protocol
//    DBG_UART -> Enable UART (8N1) debug interface
//    DBG_I2C  -> Enable I2C debug interface
`define DBG_UART
//`define DBG_I2C

// Enable the I2C broadcast address
// For multicore systems, a common I2C broadcast address
// can be given to all oMSP cores in order to
// synchronously RESET, START, STOP, or STEP all CPUs
// at once with a single I2C command.
// If you have a single openMSP430 in your system,
// this option can stay commented-out.

// Number of hardware breakpoint/watchpoint units
// (each unit contains two hardware addresses available
// for breakpoints or watchpoints):
//   - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
//   - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
//   - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
//   - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
// Please keep in mind that hardware breakpoints only
// make sense whenever the program memory is not an SRAM
// (i.e. Flash/OTP/ROM/...) or when you are interested
// in data breakpoints.
//`define  DBG_HWBRK_0
//`define  DBG_HWBRK_1
//`define  DBG_HWBRK_2
//`define  DBG_HWBRK_3

// Enable/Disable the hardware breakpoint RANGE mode
// When enabled this feature allows the hardware breakpoint
// units to stop the cpu whenever an instruction or data
// access lays within an address range.
// Note that this feature is not supported by GDB.

// Custom Program/Data and Peripheral Memory Spaces
// The following values are valid only if the
// corresponding *_SIZE_CUSTOM defines are uncommented:
// - *_SIZE : size of the section in bytes.
// - *_AWIDTH : address port width, this value must allow
// to address all WORDS of the section
// (i.e. the *_SIZE divided by 2)

// Custom Program memory (enabled with PMEM_SIZE_CUSTOM)
`define PMEM_CUSTOM_SIZE 2048

// Custom Data memory (enabled with DMEM_SIZE_CUSTOM)
`define DMEM_CUSTOM_SIZE 128

// Custom Peripheral memory (enabled with PER_SIZE_CUSTOM)
`define PER_CUSTOM_SIZE 512

// ASIC version
// When uncommented, this define will enable the
// ASIC system configuration section (see below) and
// will activate scan support for production test.
// WARNING: if you target an FPGA, leave this define
//          commented.
//`define ASIC

Design consideration at this stage are:
  • This is the expert section... so you know what your are doing anyway, right ;-)

All remaining defines located after the ASIC section in the openMSP430_defines.v file are system constants and MUST NOT be edited.

2.3.4 Parameters For Multi-Core Systems

In addition to the define file, two Verilog parameters are available to facilitate software development on multi-core systems.
For example, in a dual-core openMSP430 system, the cores can be instantiated as following:

openMSP430 #(.INST_NR (0), .TOTAL_NR(1)) openMSP430_core_0 (

openMSP430 #(.INST_NR (1), .TOTAL_NR(1)) openMSP430_core_1 (

The values of these parameters are then directly accessible by software through the CPU_NR register of the SFR peripheral.
For example, if both cores share the same program memory, the software can take advantage of this information as following:

int main(void) {
  if (CPU_NR==0x0100) {
    main_core_0(); // Main routine call for core 0
  if (CPU_NR==0x0101) {
    main_core_1(); // Main routine call for core 1

2.4 Memory mapping

As discussed earlier, the openMSP430 memory mapping is fully configurable.
The basic system configuration section allows to adjust program and data memory sizes while keeping 100% compatibility with the pre-existing linker scripts provided by MSPGCC (or any other toolchain for that matter).
However, an increasing number of users saw the 512B space available for peripherals in the standard MSP430 architecture as a limitation. Therefore, the advanced system configuration section gives the possibility to up-scale the reserved peripheral address space anywhere between 512B and 32kB. As a consequence, the data memory space will be shifted up, which means that the linker script of your favorite toolchain will have to be modified accordingly.
The following schematic should hopefully illustrate this:

Memory mapping

2.5 Interrupt mapping

The number of supported interrupts is configurable with the IRQ_xx macros. The interrupt vectors are then mapped as following:

Interrupt mapping

2.6 Pinout

The full pinout of the openMSP430 core is provided in the following table:

Port Name Direction Width Clock
Clocks & Power-Managment
cpu_en Input 1
or mclk4
Enable CPU code execution (asynchronous and non-glitchy).
Set to 1 if unused.
dco_clk Input 1 -
Fast oscillator (fast clock)
lfxt_clk Input
Low frequency oscillator (typ. 32kHz)
Set to 0 if unused.
mclk Output
Main system clock
aclk_en Output 1
smclk_en Output 1
ASIC ONLY: Fast oscillator enable

ASIC ONLY: Fast oscillator wakeup (asynchronous)
ASIC ONLY: Low frequency oscillator enable

ASIC ONLY: Low frequency oscillator wakeup (asynchronous)

ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
Set to 0 if unused.
puc_rst Output 1 mclk
Main system reset
reset_n Input 1
Reset Pin (active low, asynchronous and non-glitchy)
irq Input `IRQ_NR-21 mclk
Maskable interrupts (one-hot signal)
nmi Input 1
or mclk4
Non-maskable interrupt (asynchronous and non-glitchy)
Set to 0 if unused.
irq_acc Output `IRQ_NR-21 mclk
Interrupt request accepted (one-hot signal)
Program Memory interface
pmem_addr Output `PMEM_AWIDTH 1 mclk
Program Memory address
pmem_cen Output 1 mclk
Program Memory chip enable (low active)
pmem_din Output 16 mclk
Program Memory data input (optional 2)
pmem_dout Input 16 mclk
Program Memory data output
pmem_wen Output 2 mclk
Program Memory write byte enable (low active) (optional 2)
Data Memory interface
dmem_addr Output `DMEM_AWIDTH 1 mclk
Data Memory address
dmem_cen Output 1 mclk
Data Memory chip enable (low active)
dmem_din Output 16 mclk
Data Memory data input
dmem_dout Input 16 mclk
Data Memory data output
dmem_wen Output 2 mclk
Data Memory write byte enable (low active)
External Peripherals interface
per_addr Output 14 mclk
Peripheral address
per_din Output 16 mclk
Peripheral data input
per_dout Input 16 mclk
Peripheral data output
per_en Output 1 mclk
Peripheral enable (high active)
per_we Output 2 mclk
Peripheral write enable (high active)
Direct Memory Access interface
dma_addr Input 15 mclk
Direct Memory Access address
dma_din Input 16 mclk
Direct Memory Access data input
dma_dout Output 16 mclk
Direct Memory Access data output
dma_en Input 1 mclk
Direct Memory Access enable (high active)
dma_priority Input 1 mclk
Direct Memory Access priority (0:low / 1:high)
dma_ready Output 1 mclk
Direct Memory Access is complete
dma_resp Output 1 mclk
Direct Memory Access response (0:Okay / 1:Error)
dma_we Input 2 mclk
Direct Memory Access write byte enable (high active)
dma_wkup Input 1
ASIC ONLY: DMA Wake-up (asynchronous and non-glitchy)
Serial Debug interface
dbg_en Input 1
or mclk4
Debug interface enable (asynchronous) 3
dbg_freeze Output 1 mclk
Freeze peripherals
dbg_uart_txd Output 1 mclk
Debug interface: UART TXD
dbg_uart_rxd Input 1
Debug interface: UART RXD (asynchronous)
Input 7 mclk Debug interface: I2C Address
Input 7 mclk Debug interface: I2C Broadcast Address (for multicore systems)
Input 1 Debug interface: I2C SCL (asynchronous)
Input 1 Debug interface: I2C SDA IN (asynchronous)
Output 1 mclk Debug interface: I2C SDA OUT
ASIC ONLY: Scan enable (active during scan shifting)

ASIC ONLY: Scan mode

1: This parameter is declared in the "openMSP430_defines.v" file and defines the RAM/ROM size or the number of interrupts vectors (16, 32 or 64).
2: These two optional ports can be connected whenever the program memory is a RAM. This will allow the user to load a program through the serial debug interface and to use software breakpoints.
3: When disabled, the debug interface is hold into reset (and clock gated in ASIC mode). As a consequence, the dbg_en port can be used to reset the debug interface without disrupting the CPU execution.
4: Clock domain is selectable through configuration in the "openMSP430_defines.v" file (see Advanced System Configuration).

Note: in the FPGA configuration, the ASIC ONLY signals must be left unconnected (for the outputs) and tied low (for the inputs).

2.7 Instruction Cycles and Lengths

Please note that a detailed description of the instruction and addressing modes can be found in the MSP430x1xx Family User's Guide (Chapter 3).

The number of CPU clock cycles required for an instruction depends on the instruction format and the addressing modes used, not the instruction itself.
In the following tables, the number of clock cycles refers to the main clock (MCLK). Differences with the original MSP430 are highlighted in green (the original value being red).
  • Interrupt and Reset Cycles
Action No. of Cycles Length of Instruction
Return from interrupt (RETI) 5 1
Interrupt accepted 6 -
WDT reset 4 -
Reset (!RST/NMI) 4 -
  • Format-II (Single Operand) Instruction Cycles and Lengths
Addressing Mode No. of Cycles Length of Instruction
Rn 1 3 3 (4) 1
@Rn 3 4 4 1
@Rn+ 3 4 (5) 4 (5) 1
#N N/A 4 5 2
X(Rn) 4 5 5 2
EDE 4 5 5 2
&EDE 4 5 5 2
  • Format-III (Jump) Instruction Cycles and Lengths
All jump instructions require one code word, and take two CPU cycles to execute, regardless of whether the jump is taken or not.
  • Format-I (Double Operand) Instruction Cycles and Lengths
Addressing Mode No. of Cycles Length of Instruction
Src Dst
Rn Rm 1 1
PC 2 1
x(Rm) 4 2
EDE 4 2
&EDE 4 2
@Rn Rm 2 1
PC 3 (2) 1
x(Rm) 5 2
EDE 5 2
&EDE 5 2
@Rn+ Rm 2 1
PC 3 1
x(Rm) 5 2
EDE 5 2
&EDE 5 2
#N Rm 2 2
PC 3 2
x(Rm) 5 3
EDE 5 3
&EDE 5 3
x(Rn) Rm 3 2
PC 3 (4) 2
x(Rm) 6 3
EDE 6 3
&EDE 6 3
EDE Rm 3 2
PC 3 (4) 2
x(Rm) 6 3
EDE 6 3
&EDE 6 3
&EDE Rm 3 2
PC 3 2
x(Rm) 6 3
EDE 6 3
&EDE 6 3

2.8 Serial Debug Interface

All the details about the Serial Debug Interface are located here.

2.9 Benchmark results

2.9.1 Dhrystone (DMIPS/MHz)

Dhrystone is known for being susceptible to compiler optimizations (among other issues).
However, as it is still quite a popular metric, some results are provided here (ranging from 0.30 to 0.45 DMIPS/MHz depending on the compiler version and options).
Note that the used C-code is available in the repository here and here.

Dhrystone flavor Compiler options -Os -O2 -O3
Compiler version
Dhrystone v2.1
(common version)
mspgcc v4.4.5 0.30 0.32 0.33
mspgcc v4.6.3 0.37 0.39 0.40
Dhrystone v2.1
(MCU adapted)
mspgcc v4.4.5 0.30 0.30 0.31
mspgcc v4.6.3 0.37 0.44 0.45

2.9.2 CoreMark (CoreMark/MHz)

CoreMark tries to address most of Dhrystone's pitfall by preventing the compiler to optimize some code away and using "real-life" algorithm.
Note that the used C-code is available in the repository here.

Compiler options -Os -O2 -O3
Compiler version
CoreMark v1.0
(official version)
mspgcc v4.4.5 0.78 0.85 0.83
mspgcc v4.6.3 0.74 0.91 0.87