Nov 6, 2017Fix documentation typo with 'BCSCTLx/DCOCTL' names and addresses.Girard, Olivier
Nov 6, 2017Fix documentation typo with 'per_we' port.Girard, Olivier
Dec 7, 2016test editAdmin, OpenCores
Dec 5, 2016Update typo in the instruction length table documentationGirard, Olivier
Aug 17, 2016Add DE0_NANO_SOC board in the FPGA section (including demo of the openGFX430)Girard, Olivier
Aug 17, 2016DE1 board FPGA example moved to the OBSOLETE directory.Girard, Olivier
Aug 1, 2016Minor update to overview HTMLGirard, Olivier
Jul 1, 2015Add DMA interfaceGirard, Olivier
May 7, 2015DMA interface support coming soon...Girard, Olivier
Jan 21, 2015Major verification and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains.Girard, Olivier
Oct 7, 2014Update GDB-Proxy to support new GCC/GDB compiler version from RedHat/TIGirard, Olivier
Dec 17, 2013Number of supported IRQs is now configurable to 14 (default), 30 or 62.Girard, Olivier
Feb 25, 2013Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme. Thanks to Sebastien Van Cauwenberghe's contribution :-)Girard, Olivier
Nov 27, 2012Update documentation with new I2C based serial debug interfaceGirard, Olivier
Oct 15, 2012The serial debug interface now supports the I2C protocol (in addition to the UART)Girard, Olivier
Jun 8, 2012Update donation buttons for proper rendering of the "Overview" pageGirard, Olivier
Jun 8, 2012Fixed some typo in documentationGirard, Olivier
Jun 8, 2012Add donation buttonsGirard, Olivier
Jun 6, 2012Fixed typoGirard, Olivier
Jun 5, 2012Add Dhrystone & CoreMark benchmark results.Girard, Olivier
Apr 22, 2012Add Google+ linkGirard, Olivier
Mar 22, 2012ASIC proven :-)Girard, Olivier
Mar 22, 2012Adjust image size for the HTML documentationGirard, Olivier
Mar 22, 2012Add full ASIC support (low-power modes, DFT, ...). Improved serial debug interface reliability.Girard, Olivier
Oct 24, 2011ASIC teaser :-)Girard, Olivier
Oct 19, 2011Fixed failing image links in the online documentation.Girard, Olivier
Aug 9, 2011testGirard, Olivier
Jul 25, 2011Thanks to Ricardo Ribalda Delgado an new FPGA example is available: Avnet Spartan-6 LX9 microboardGirard, Olivier
Jun 23, 2011To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license.Girard, Olivier
Jun 7, 2011Update online documentation to reflect the latest design status.Girard, Olivier
May 20, 2011Note that the per_addr bus width goes from 8 to 14 bits and that your custom peripherals address decoders must be updated accordingly.Girard, Olivier
May 20, 2011Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).Girard, Olivier
Mar 1, 2011Update online documentation with Actel's FPGA implementation exampleGirard, Olivier
Feb 24, 2011Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators: Icarus Verilog, Cver, Verilog-XL, NCVerilog, Modelsim Girard, Olivier
Feb 20, 2011Bug Fix (SVN revision 92): When the CPU is Halted through the serial debug interface and if an IRQ occures during this time, then the CPU will go wild when the CPU goes out of halt mode. Girard, Olivier
Feb 12, 2011Software development tools update: new Minidebug interface, Intel-HEX files are now supportedGirard, Olivier
Dec 16, 2010Add Actel ProASIC3 example project with SpaceWar oscilloscope game demo :-)Girard, Olivier
Aug 28, 2010Update serial debug interface to support memories whose sizes are not a power of 2.Girard, Olivier
Aug 1, 2010Expand configurability of the program and data memory sizes.Girard, Olivier
May 15, 2010add link to discussion groupGirard, Olivier
Apr 25, 2010The openMSP430 is now listed by TI on its open source projects list:, Olivier
Mar 7, 2010Add online documentation section: Area and Speed analysisGirard, Olivier
Mar 7, 201016x16 Hardware Multiplier is available :-)Girard, Olivier
Feb 1, 2010Exclude the range mode from the Hardware breakpoint units by default as it is not used by GDB.Girard, Olivier
Jan 22, 2010Add online documentation section: Integration and connectivityGirard, Olivier
Jan 4, 2010change image properties in html documentation for proper rendering in google Chrome browserGirard, Olivier
Dec 29, 2009Update the online documentation to reflect the latest Verilog changes.Girard, Olivier
Dec 29, 2009In order to avoid confusion, the following changes have been implemented to the Verilog code: - renamed the "rom_*" ports and defines to "pmem_*" (program memory). - renamed the "ram_*" ports and defines to "dmem_*" (data memory). In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.Girard, Olivier
Dec 29, 2009To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix.Girard, Olivier
Dec 27, 2009Add Altera Cyclone II FPGA project example (thanks to Vadim Akimov contribution) + diverse minor updates in the documentation.Girard, Olivier
Dec 27, 2009HTML documentation (Overview): Update limitation sectionGirard, Olivier
Sep 20, 2009Windows Users: Some batch files have been created so that you can now run the FPGA Xilinx flow from windows (assuming that ISE is installed on your system).Girard, Olivier
Aug 30, 2009The defines are now directly included (with the `include construct) in the Verilog files.Girard, Olivier
Aug 30, 2009replaced "" with "openMSP430_defines.v"Girard, Olivier
Aug 25, 2009Added the "Specification done" tagGirard, Olivier
Aug 17, 2009Updated some links in the "Core" documentationGirard, Olivier
Aug 17, 2009Updated some linksGirard, Olivier
Aug 4, 2009Updated all source code headers with SVN keywordsGirard, Olivier
Aug 4, 2009Completed documentationGirard, Olivier
Jul 12, 2009Serial debug interface documentation completedGirard, Olivier
Jul 1, 2009Project has been uploaded to the SVN repository. Documentation on going.Girard, Olivier