OpenCores

Peripherals

Table of content

1. Introduction

In addition to the CPU core itself, several peripherals are also provided and can be easily connected to the core during integration.

2. Peripherals

2.1 System Peripherals

In addition to the CPU core itself, several peripherals are also provided and can be easily connected to the core during integration. The followings are directly integrated within the core because of their tight links with the CPU.
It is to be noted that ALL system peripherals support both ASIC and FPGA versions.

2.1.1 Basic Clock Module: FPGA


In order to make an FPGA implementation as simple as possible (ideally, a non-professional designer should be able to do it), clock gates are not used in this design configuration and neither are clock muxes.
With these constrains, the Basic Clock Module is implemented as following:

Clock structure diagram
Note: CPUOFF doesn't switch MCLK off and will instead bring the CPU state machines in an IDLE state while MCLK will still be running.

In order to 'clock' a register with ACLK or SMCLK, the following structure needs to be implemented:

Clock implementation example

For example, the following Verilog code would implement a counter clocked with SMCLK:



reg [7:0] test_cnt;

always @ (posedge mclk or posedge puc_rst)
if (puc_rst) test_cnt else if (smclk_en) test_cnt


Register Description (FPGA)

Register Name Address Bit Field
7 6 5 4 3 2 1 0
DCOCTL 0x0056 not implemented
BCSCTL1 0x0057 unused DIVAx unused
BCSCTL2 0x0058 unused SELS DIVSx unused
  • BCSCTL1.DIVAx : ACLK_EN divider (1/2/4/8)
  • BCSCTL2.SELS   : SMCLK_EN clock selection (0:DCO_CLK / 1:LFXT_CLK)
  • BCSCTL2.DIVSx : SMCLK_EN divider (1/2/4/8)

2.1.2 Basic Clock Module: ASIC


When targeting an ASIC, up to all clock management options available in the MSP430x1xx Family User's Guide (Chapter 4) can be included:

Clock structure diagram
Additional info can be found in the ASIC implementation section.

Register Description (ASIC)

Register Name Address Bit Field
7 6 5 4 3 2 1 0
DCOCTL 0x0056 not implemented
BCSCTL1 0x0057 unused DIVAx DMA_SCG1 DMA_SCG0 DMA_OSCOFF DMA_CPUOFF
BCSCTL2 0x0058 SELMx unused DIVMx SELS DIVSx unused
  • BCSCTL1.DIVAx     : ACLK clock divider (1/2/4/8)
  • BCSCTL1.DMA_SCG1    : Restore SMCLK with DMA wakeup
  • BCSCTL1.DMA_SCG0    : Restore DCO oscillator with DMA wakeup
  • BCSCTL1.DMA_OSCOFF : Restore LFXT oscillator with DMA wakeup
  • BCSCTL1.DMA_CPUOFF : Restore MCLK with DMA wakeup
  • BCSCTL2.SELMx      : MCLK clock selection (0:DCO_CLK / 1:LFXT_CLK)
  • BCSCTL2.DIVMx      : MCLK clock divider (1/2/4/8)
  • BCSCTL2.SELS       : SMCLK clock selection (0:DCO_CLK / 1:LFXT_CLK)
  • BCSCTL2.DIVSx     : SMCLK clock divider (1/2/4/8)

2.1.3 SFR

Following the MSP430x1xx Family User's Guide, this peripheral implements flags and interrupt enable bits for the Watchdog Timer and NMI:

Register Name Address Bit Fields
7
6
5
4
3
2
1
0
IE1
0x0000  Reserved
NMIIE 1   Reserved  WDTIE 2
IFG1
0x0002 Reserved
NMIIFG 1 Reserved WDTIFG 2

1: These fields are not available if the NMI is excluded (see openMSP430_defines.v )
2: These fields are not available if the Watchdog is excluded (see openMSP430_defines.v )

In addition, three 16-bit read-only registers have been added in order to let the software know with which version of the openMSP430 it is running:

Register Name Address Bit Field
1514 1312 1110 9 8 7 6 5 4 3 2 1 0
CPU_ID_LO 0x0004 PER_SPACE USER_VERSION ASIC CPU_VERSION
CPU_ID_HI 0x0006 PMEM_SIZE DMEM_SIZE MPY
CPU_NR 0x0008 CPU_TOTAL_NR CPU_INST_NR

 
  • CPU_VERSION
  • : Current CPU version
     
  • ASIC
  • : Defines if the ASIC specific features are enabled in the current openMSP430 implementation.
     
  • USER_VERSION
  • : Reflects the value defined in the openMSP430_defines.v file.
     
  • PER_SPACE
  • : Peripheral address space for the current implementation (byte size = PER_SPACE*512)
     
  • MPY
  • : This bit is set if the hardware multiplier is included in the current implementation
     
  • DMEM_SIZE
  • : Data memory size for the current implementation (byte size = DMEM_SIZE*128)
     
  • PMEM_SIZE
  • : Progam memory size for the current implementation (byte size = PMEM_SIZE*1024)
     
  • CPU_INST_NR
  • : Current oMSP instance number (for multicore systems)
     
  • CPU_TOTAL_NR
  • : Total number of oMSP instances-1 (for multicore systems)

    Note: attentive readers will have noted that CPU_ID_LO, CPU_ID_HI and CPU_NR are identical to the Serial Debug Interface register counterparts.

    2.1.4 Watchdog Timer

    100% of the features advertised in the MSP430x1xx Family User's Guide (Chapter 10) have been implemented.

    The following parameter in the openMSP430_defines.v file controls if the watchdog timer should be included or not:




    //-------------------------------------------------------
    // Include/Exclude Watchdog timer
    //-------------------------------------------------------
    // When excluded, the following functionality will be
    // lost:
    //        - Watchog (both interval and watchdog modes)
    //        - NMI interrupt edge selection
    //        - Possibility to generate a software PUC reset
    //-------------------------------------------------------
    `define WATCHDOG

    2.1.5 16x16 Hardware Multiplier

    100% of the features advertised in the MSP430x1xx Family User's Guide (Chapter 7) have been implemented.

    The following parameter in the openMSP430_defines.v file controls if the hardware multiplier should be included or not:




    // Include/Exclude Hardware Multiplier
    `define MULTIPLIER

    2.2 External Peripherals

    The external peripherals labeld with the "FPGA ONLY" tag do not contain any clock gate nor clock muxes and are clocked with MCLK only. This mean that they don't support any of the low power modes and therefore are most likely not suited for an ASIC implementation.

    2.2.1 Digital I/O (FPGA ONLY)

    100% of the features advertised in the MSP430x1xx Family User's Guide (Chapter 9) have been implemented.

    The following Verilog parameters will enable or disable the corresponding ports in order to save area (i.e. FPGA utilization):




    parameter P1_EN = 1'b1; // Enable Port 1
    parameter P2_EN = 1'b1; // Enable Port 2
    parameter P3_EN = 1'b0; // Enable Port 3
    parameter P4_EN = 1'b0; // Enable Port 4
    parameter P5_EN = 1'b0; // Enable Port 5
    parameter P6_EN = 1'b0; // Enable Port 6

    They can be updated as following during the module instantiation (here port 1, 2 and 3 are enabled):




    gpio #(.P1_EN(1),
    .P2_EN(1),
    .P3_EN(1),
    .P4_EN(0),
    .P5_EN(0),
    .P6_EN(0)) gpio_0 (

    The full pinout of the GPIO module is provided in the following table:

    Port Name Direction Width Description
    Clocks & Resets
    mclk Input 1 Main system clock
    puc_rst Input 1 Main system reset
    Interrupts
    irq_port1 Output 1 Port 1 interrupt
    irq_port2 Output 1 Port 2 interrupt
    External Peripherals interface
    per_addr Input 8 Peripheral address
    per_din Input 16 Peripheral data input
    per_dout Output 16 Peripheral data output
    per_en Input 1 Peripheral enable (high active)
    per_we Input 2 Peripheral write enable (high active)
    Port 1
    p1_din Input 8 Port 1 data input
    p1_dout Output 8 Port 1 data output
    p1_dout_en Output 8 Port 1 data output enable
    p1_sel Output 8 Port 1 function select
    Port 2
    p2_din Input 8 Port 2 data input
    p2_dout Output 8 Port 2 data output
    p2_dout_en Output 8 Port 2 data output enable
    p2_sel Output 8 Port 2 function select
    Port 3
    p3_din Input 8 Port 3 data input
    p3_dout Output 8 Port 3 data output
    p3_dout_en Output 8 Port 3 data output enable
    p3_sel Output 8 Port 3 function select
    Port 4
    p4_din Input 8 Port 4 data input
    p4_dout Output 8 Port 4 data output
    p4_dout_en Output 8 Port 4 data output enable
    p4_sel Output 8 Port 4 function select
    Port 5
    p5_din Input 8 Port 5 data input
    p5_dout Output 8 Port 5 data output
    p5_dout_en Output 8 Port 5 data output enable
    p5_sel Output 8 Port 5 function select
    Port 6
    p6_din Input 8 Port 6 data input
    p6_dout Output 8 Port 6 data output
    p6_dout_en Output 8 Port 6 data output enable
    p6_sel Output 8 Port 6 function select

    2.2.2 Timer A (FPGA ONLY)

    100% of the features advertised in the MSP430x1xx Family User's Guide (Chapter 11) have been implemented.

    The full pinout of the Timer A module is provided in the following table:

    Port Name Direction Width Description
    Clocks, Resets & Debug
    mclk Input 1 Main system clock
    aclk_en Input 1 ACLK enable (from CPU)
    smclk_en Input 1 SMCLK enable (from CPU)
    inclk Input 1 INCLK external timer clock (SLOW)
    taclk Input 1 TACLK external timer clock (SLOW)
    puc_rst Input 1 Main system reset
    dbg_freeze Input 1 Freeze Timer A counter
    Interrupts
    irq_ta0 Output 1 Timer A interrupt: TACCR0
    irq_ta1 Output 1 Timer A interrupt: TAIV, TACCR1, TACCR2
    irq_ta0_acc Input 1 Interrupt request TACCR0 accepted
    External Peripherals interface
    per_addr Input 8 Peripheral address
    per_din Input 16 Peripheral data input
    per_dout Output 16 Peripheral data output
    per_en Input 1 Peripheral enable (high active)
    per_we Input 2 Peripheral write enable (high active)
    Capture/Compare Unit 0
    ta_cci0a Input 1 Timer A capture 0 input A
    ta_cci0b Input 1 Timer A capture 0 input B
    ta_out0 Output 1 Timer A output 0
    ta_out0_en Output 1 Timer A output 0 enable
    Capture/Compare Unit 1
    ta_cci1a Input 1 Timer A capture 1 input A
    ta_cci1b Input 1 Timer A capture 1 input B
    ta_out1 Output 1 Timer A output 1
    ta_out1_en Output 1 Timer A output 1 enable
    Capture/Compare Unit 2
    ta_cci2a Input 1 Timer A capture 2 input A
    ta_cci2b Input 1 Timer A capture 2 input B
    ta_out2 Output 1 Timer A output 2
    ta_out2_en Output 1 Timer A output 2 enable

    Note: for the same reason as with the Basic Clock Module FPGA version, the two additional clock inputs (TACLK and INCLK) are internally synchronized with the MCLK domain. As a consequence, TACLK and INCLK should be at least 2 times slowlier than MCLK, and if these clock are used toghether with the Timer A output unit, some jitter might be observed on the generated output. If this jitter is critical for the application, ACLK and INCLK should idealy be derivated from DCO_CLK.