Hi ,
While compiling the code the in Xilinx ISE , I got the following error
ERROR:HDLCompiler:267 - "D:\S2S\SVN\opencores\openmsp430\fpga\xilinx_custom_lx9board\rtl\verilog\omsp_uart.v" Line 300: Cannot find port data_meta on this module
It appears that the omsp_sync_cell module dont have the port "data_meta"
Thansk
Hi, you probably mixed-up version of the omsp_uart file with the rest of the openMS430 project. Make sure you get the latest file version of the UART (it can be find in each FPGA project example).
Olivier