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unsynchronized peripheral bus bits in TimerA #27
Closed ymatra opened this issue almost 9 years ago
ymatra commented almost 9 years ago

Hi,

I noticed that e.g. ta_cci0b on the timer module is mixed to the per_dout port without synchronization. There is a synchroniser on this signal (sync_cell_cci0), so maybe cci0_s can be used in tacctl0_full instead of cci0? I guess similar logic is present on other signals.

Alternatively, all async inputs could be synchronized first before use in the module. This would cost some additional synchro flops.

Cheers, Johan for ICsense N.V.

olivier.girard commented over 7 years ago

Hi,

thanks a lot for the report Johan. I have updated the core some time ago (exactly what you proposed) in version r204: http://opencores.org/websvn,filedetails?repname=openmsp430&path=/openmsp430/trunk/ChangeLog_core.txt

Olivier

olivier.girard closed this over 7 years ago

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