Maximum/Minimum binary tree finder

Project maintainers

Atalla, Shadi

Details

Name: parallel_search_for_maximum_weight
Created: Oct 4, 2010
Updated: Oct 5, 2010
SVN Updated: Oct 7, 2010
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved

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Other project properties

Category:Arithmetic core
Language:VHDL
Development status:Beta
Additional info:Design done
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

the aim of this design to build combinatorial digital circuit to find in fast parallel the maximum or the minimum of set of given set data where number of entries = N, can be configured at compile time and also the width = M of each entry.

the design idea based on binary tree structure, where there are Log_2(N) levels in the tree, the best values of N where
Log_2(N) = integer numbers like N = ( 4, 8, 16, 32, 64,...) where Log_2(N) = {2, 3, 4, 5, ...}. but to support general values of N like 29 the design will be Log_2(29)+1 which Log_2(32) where the values 30,31,32 is padded with zero's. for the width of each value the best is the even numbers but in case of odd the width is incremented by 1 and the LSB is = '0'.

Files description

File name	description
basic_size.vhd	Define N = size of the data set, M which the WIDTH of each of Value
basic_component.vhd	Define all the component of the design , no need to change it
parallel_find_top.vhd	the top level file of the design
mux_sel.vhd	compare and select the value of maximum, no need to change it
Ripple.vhd	build the compare function based on ripple , no need to change it
Result.vhd	build the select the answer , no need to change it(but here is possible to change from maximum and minimum, i will make this configurable)
carry_cell_NAND.vhd	basic cell of the compare based on NAND gates,no need to change it
carry_cell_NOR.vhd	basic cell of the compare based on NOR gates,no need to change it