OpenCores

PWM :: Overview



Project maintainers

Details

Name: pwm
Created: Sep 19, 2012
Updated: Oct 13, 2012
SVN Updated: Oct 5, 2012
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star0you like it: star it!

Other project properties

Category:Other
Language:Verilog
Development status:Alpha
Additional info:Design done, FPGA proven, Specification done
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

Pulse Width Modulator
Features
• Work as one PWM or one timer.
• 16 bits main counter.
• PWM/Timer can choose between Wishbone interface clock or external clock as working clock.
• PWM can choose between dedicated duty cycle input or internal register as source of duty cycle.
• Duty cycle and period can be changed at runtime.
• Hosted through Wishbone slave interface.
• Working clock's frequency can be divided to at most 1/65535 of original frequency.
• Period register also serves as timer target register when module is in timer mode.
© copyright 1999-2018 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.