Lynn, Owen

Scratch DDR SDRAM Controller

NOTE: Warning, this is a double post to make sure I get a receiver and can do a Commit soon. Also posted in the other-section of the forum for more input!

I'm looking into building up a file structure for the new scratch ddr-controller which permits separating and sharing files between several synthesis projects. For now everything is working fine, I can build both the 500E and 1600E projects from the same physical disk files by using relative paths in the ISE 11.2 XISE-files. Having this structure will probably demand text-editing the XISE-file (XML-file = simple) each time someone add files but I think it's worth it.

For now it looks like this locally:
-[trunk]
   scratch.vhd
   ... and all other files as before...
  -[boards]
    -[Microblaze1600E]
       Microblaze1600E.xise
       Microblaze1600E.ucf
    -[StarterKit500E]
       StarterKit500E.xise
       StarterKit500E.ucf

Is there a OpenCores-standard for laying out the directory structure? Then this should probably be followed instead. 

By looking at for example MilkyMist at: 
http://github.com/lekernel/milkymist

they use a deeper structure with all reusable cores under /cores/.../ and under their respective names. They also use a /boards/.../ directory in where they also separate synthesis files and board-specific rtl. One step further would  be to support several versions of the environments (10.1, 11.x) and of course also have support of several vendors (/xilinx/ /altera/ /lattice/ ) but I think this will have to wait until/if other people joins.

I kind of like the shallow one I describe above to start with! It can be reworked later if there are more interested parties.

File structure in SVN

Thank you for sharing the complete project, this is great material and gives me some more to go on why is does not work with my card yet!

The project does not work for me, there are no LED's lighting up just now, but I'm working on it. The only difference I found and changed from your TAR-file is:

NET "dram_addr<4>"  LOC = "E4" |IOSTANDARD = SSTL2_I; #F4

The bit 4 address line is located at F4 for 500E and E4 for 1600E. I will look into details if there are something more, but looks OK for now.

But both "Behavior Simulation" and "Post-Route Simulation" gives timing errors.

-snip-
Finished circuit initialization process.
at 2269 ps(3), Instance /scratch_isim_tb/uut/SDRAM_READER_reg1_6/ : Warning: /X_FF SETUP  Low VIOLATION ON CE WITH RESPECT TO CLK;
  Expected := 0.651 ns; Observed := 0.169 ns; At : 2.269 ns

WARNING: at 24330100 ps: Timing violation in /scratch_isim_tb/DRAM_CHIP/  $setuphold<hold>( Clk:24330100 ps, Addr:24330100 ps,750 ps,750 ps)
-snip-

Is this important or can it just be overlooked, I'm not sure.. Isn't the meaning of the scratch_isim_tb.vhd to actually present the correct answer on the dram_dq just as the real FPGA-implementation would?

scratch_isim_tb.vhd

Thanks for sharing this! After reading LOTS of posts with 500E/1600E Starter Kits owner who struggles with getting the DDR to dance foxtrot I think maybe your super-simple core could be the OPTIMAL solution! I will try to help you out as much as possible to get this baby running!

I've tried you the core on my Digilent/Xilinx Microblaze Starter Kit (featuring a 1600E) but cannto get the LED's to light up.

An idea to get more users of the core an simpler start-up for us non-pro's is to include a synth-library with ready-made ISE-project files which is possible to run right-away. I know there are lots of different versions and so on, but at least target the last released or best working just now. One of the problems that this may overcome is to get a working UCF-constraint file which is a job in itself.

Is there some signals missing/being incorrectly named in the committed last version? 50Mhz vs. 100Mhz maybe changed in one place but not in the other.. or have the DCM been cut away? Maybe this should be done in some other way.. 

In my case I've put together a UCF that maybe is correct for my board, included a 50=>100Mhz DCM on the top-level but it does not work. The 500E and 1600E shall have the same DDR-RAM connection but it seems to be missing some important signals: CAS/RAS/DQS_Div0 or is these not important when using 
the chip in simple ways? I'm a complete idiot with SDR/DDR to day.

If you could commit your whole project with all synth-specific files in a Xilinx/500E under folder that would make my day! :-)

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Scratch DDR SDRAM Controller