Lynn, Owen

Scratch DDR SDRAM Controller

There appears to be a bug in the control logic that allows the core to lock up.  In either the read or write command, the first state sets an op and waits for an  ack.  Then the next state waits for busy_n to be released.  Since the idle state is set up to clear the busy_n and to check for read or write commands (which set the busy_n) the core can get caught in STATE2 (for write) or STATE4 (for read)  There are lots of ways this could be fixed.  One way would be to clear the op code after it has been acknowledged.  This would need to be done in both STATE1 and STATE3, with the STATE1 code shown below.

when STATE1 =>
	op <= "10";
	addr <= "0000000000"& x"6001";
	data_i <= "11110001";
	if (op_ack = '1') then
-- begin new code
		op <= "00";
-- end new code          
		dram_driver_state <= STATE2;
	end if;

Thanks,

James

op not cleared before second part of read or write command

Here is an patch to clean up a little bit with librarys:

Index: sdram_support.vhd
===================================================================
--- sdram_support.vhd	(revision 24)
+++ sdram_support.vhd	(working copy)
@@ -22,13 +22,7 @@
 ----------------------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
 
 entity cmd_bank_addr_switch is
 	port(
@@ -57,13 +51,8 @@
 
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.numeric_std.ALL;
 
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
-library UNISIM;
-use UNISIM.VComponents.all;
 
 entity wait_counter is
 	generic(
@@ -79,7 +68,7 @@
 
 architecture impl of wait_counter is
 	
-	signal reg : std_logic_vector(BITS-1 downto 0);
+	signal reg : unsigned(BITS-1 downto 0) := (others => '0');
 	
 begin
 
@@ -87,7 +76,7 @@
 	begin
 		if (rst = '1') then
 			done <= '0';
-			reg <= CONV_STD_LOGIC_VECTOR(CLKS, BITS);
+			reg <= to_unsigned(CLKS, BITS);
 		elsif (rising_edge(clk)) then
 			if (reg > x"00") then
 				done <= '0';
@@ -103,13 +92,11 @@
 
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
 library UNISIM;
-use UNISIM.VComponents.all;
+use UNISIM.VComponents.dcm_sp;
+use UNISIM.VComponents.bufg;
+use UNISIM.VComponents.oddr2;
 
 entity sdram_dcm is
 	port(
@@ -235,13 +222,9 @@
 
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
 library UNISIM;
-use UNISIM.VComponents.all;
+use UNISIM.VComponents.oddr2;
 
 -- just a 2 bit wide ODDR2
 entity oddr2_2 is
@@ -295,13 +278,9 @@
 
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
 library UNISIM;
-use UNISIM.VComponents.all;
+use UNISIM.VComponents.oddr2;
 
 -- just a 3 bit wide ODDR2
 entity oddr2_3 is
@@ -371,13 +350,7 @@
 
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
-library UNISIM;
-use UNISIM.VComponents.all;
 
 -- 2 oddr2_2's
 entity oddr2_4 is
@@ -434,13 +407,9 @@
 	
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
 library UNISIM;
-use UNISIM.VComponents.all;
+use UNISIM.VComponents.oddr2;
 
 -- one ODDR2 and 3 4-bit oddr2_4's
 entity oddr2_13 is
@@ -527,13 +496,7 @@
 
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
-library UNISIM;
-use UNISIM.VComponents.all;
 
 -- 4 4-bit oddr2_4's
 entity oddr2_16 is
@@ -614,13 +577,7 @@
 
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
-library UNISIM;
-use UNISIM.VComponents.all;
 
 entity inout_switch_2 is
 	port (
@@ -638,13 +595,7 @@
 
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
-library UNISIM;
-use UNISIM.VComponents.all;
 
 entity inout_switch_16 is
 	port (
Index: sdram_writer.vhd
===================================================================
--- sdram_writer.vhd	(revision 24)
+++ sdram_writer.vhd	(working copy)
@@ -22,14 +22,7 @@
 ----------------------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
 -- Uses ODDR2 registers to generate the required DDR signals. Don't have to be as
 --  careful with the timings as with sdram_reader, but you need to be able to feed
 --  the ODDR2's within their setup and hold windows. Or very very hilarious things
Index: sdram.vhd
===================================================================
--- sdram.vhd	(revision 24)
+++ sdram.vhd	(working copy)
@@ -22,8 +22,6 @@
 ----------------------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 ---- Uncomment the following library declaration if instantiating
 ---- any Xilinx primitives in this code.
Index: scratch.vhd
===================================================================
--- scratch.vhd	(revision 24)
+++ scratch.vhd	(working copy)
@@ -22,10 +22,9 @@
 ----------------------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
 library UNISIM;
-use UNISIM.VComponents.all;
+use UNISIM.VComponents.bufg;
+use UNISIM.VComponents.dcm_sp;
 
 
 entity scratch is
Index: sdram_reader.vhd
===================================================================
--- sdram_reader.vhd	(revision 24)
+++ sdram_reader.vhd	(working copy)
@@ -21,14 +21,7 @@
 ----------------------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
 -- I strongly suggest you run this in the post-PAR simulator first and then start
 --  making changes to it after looking at what goes on at the post-PAR level. Don't
 --  say I didn't warn you. 
@@ -80,4 +73,4 @@
 		end if;
 	end process;
 
-end impl;
\ No newline at end of file
+end impl;
Index: sdram_init.vhd
===================================================================
--- sdram_init.vhd	(revision 24)
+++ sdram_init.vhd	(working copy)
@@ -22,14 +22,7 @@
 ----------------------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
 entity sdram_init is
 	port(
 		clk_000 : in std_logic;
Index: scratch_isim_tb.vhd
===================================================================
--- scratch_isim_tb.vhd	(revision 24)
+++ scratch_isim_tb.vhd	(working copy)
@@ -29,11 +29,8 @@
 --------------------------------------------------------------------------------
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
-USE ieee.std_logic_unsigned.all;
 USE ieee.numeric_std.ALL;
  
-library UNISIM;
-use UNISIM.VComponents.all;
 
 ENTITY scratch_isim_tb IS
 	port(
@@ -145,27 +143,7 @@
 	);
 		  
 
-   -- Clock process definitions
-   clk_process :process
-   begin
-		clk <= '0';
-		wait for clk_period/2;
-		clk <= '1';
-		wait for clk_period/2;
-   end process;
- 
+   clk <= not clk after clk_period/2;
+   rst <= '1', '0' after 5 * clk_period;
 
-   -- Stimulus process
-   stim_proc: process
-   begin		
-      -- hold reset state for 100ms.
-      wait for 100ms;	
-
-      wait for clk_period*10;
-
-      -- insert stimulus here 
-
-      wait;
-   end process;
-
 END;

switch to std librarys and library cleanup

The DCM didn't lok in simulation beacuse the reset is fixed to '0'.

Add the following line in scratch_isim_tb.vhd will help:

rst <= '1', '0' after 5 * clk_period;

regards

DCM dont lock

Hi everyone,

I downloaded that project, used ISE11.5 first and after downloading the bit-file to the spartan e3 starterboard no led were flashing.
I downgraded to ISE11.1 and tried it again and then it worked.
But downloading the same bit-file at a different time nothing is working.
I thought about a problem with my board and tried a microblaze design, there the ddr is working reliable.

The chance the leds flashes are about 5%.
So is that a bug during initialization, does anyone else have the same problem?
Any suggestions?

Thank you.

In regards
Steffen Mauch

not working reliable

I saw another post mentioning that to use this controller, it requires an external 100mhz clock.  Is this true?

It synthesized, etc etc and programmed on my Spartan3E 500 board like a charm! One of the few projects that does that direct-from-download w/ no tweaking.

I'm getting L->R on the LEDS ON ON ON ON OFF ON OFF ON.

In order to use this code, where does a hobbyist get a 100mhz clock?  I mean for use with the xilinx starter kit?  I suppose I need some type of function generator?

Appreciate any help!

Keith

Does this require external 100mhz clock?

NOTE: Warning, this is a double post to make sure I get a receiver and can do a Commit soon. Also posted in the other-section of the forum for more input!

I'm looking into building up a file structure for the new scratch ddr-controller which permits separating and sharing files between several synthesis projects. For now everything is working fine, I can build both the 500E and 1600E projects from the same physical disk files by using relative paths in the ISE 11.2 XISE-files. Having this structure will probably demand text-editing the XISE-file (XML-file = simple) each time someone add files but I think it's worth it.

For now it looks like this locally:
-[trunk]
   scratch.vhd
   ... and all other files as before...
  -[boards]
    -[Microblaze1600E]
       Microblaze1600E.xise
       Microblaze1600E.ucf
    -[StarterKit500E]
       StarterKit500E.xise
       StarterKit500E.ucf

Is there a OpenCores-standard for laying out the directory structure? Then this should probably be followed instead. 

By looking at for example MilkyMist at: 
http://github.com/lekernel/milkymist

they use a deeper structure with all reusable cores under /cores/.../ and under their respective names. They also use a /boards/.../ directory in where they also separate synthesis files and board-specific rtl. One step further would  be to support several versions of the environments (10.1, 11.x) and of course also have support of several vendors (/xilinx/ /altera/ /lattice/ ) but I think this will have to wait until/if other people joins.

I kind of like the shallow one I describe above to start with! It can be reworked later if there are more interested parties.

File structure in SVN

Thank you for sharing the complete project, this is great material and gives me some more to go on why is does not work with my card yet!

The project does not work for me, there are no LED's lighting up just now, but I'm working on it. The only difference I found and changed from your TAR-file is:

NET "dram_addr<4>"  LOC = "E4" |IOSTANDARD = SSTL2_I; #F4

The bit 4 address line is located at F4 for 500E and E4 for 1600E. I will look into details if there are something more, but looks OK for now.

But both "Behavior Simulation" and "Post-Route Simulation" gives timing errors.

-snip-
Finished circuit initialization process.
at 2269 ps(3), Instance /scratch_isim_tb/uut/SDRAM_READER_reg1_6/ : Warning: /X_FF SETUP  Low VIOLATION ON CE WITH RESPECT TO CLK;
  Expected := 0.651 ns; Observed := 0.169 ns; At : 2.269 ns

WARNING: at 24330100 ps: Timing violation in /scratch_isim_tb/DRAM_CHIP/  $setuphold<hold>( Clk:24330100 ps, Addr:24330100 ps,750 ps,750 ps)
-snip-

Is this important or can it just be overlooked, I'm not sure.. Isn't the meaning of the scratch_isim_tb.vhd to actually present the correct answer on the dram_dq just as the real FPGA-implementation would?

scratch_isim_tb.vhd

Thanks for sharing this! After reading LOTS of posts with 500E/1600E Starter Kits owner who struggles with getting the DDR to dance foxtrot I think maybe your super-simple core could be the OPTIMAL solution! I will try to help you out as much as possible to get this baby running!

I've tried you the core on my Digilent/Xilinx Microblaze Starter Kit (featuring a 1600E) but cannto get the LED's to light up.

An idea to get more users of the core an simpler start-up for us non-pro's is to include a synth-library with ready-made ISE-project files which is possible to run right-away. I know there are lots of different versions and so on, but at least target the last released or best working just now. One of the problems that this may overcome is to get a working UCF-constraint file which is a job in itself.

Is there some signals missing/being incorrectly named in the committed last version? 50Mhz vs. 100Mhz maybe changed in one place but not in the other.. or have the DCM been cut away? Maybe this should be done in some other way.. 

In my case I've put together a UCF that maybe is correct for my board, included a 50=>100Mhz DCM on the top-level but it does not work. The 500E and 1600E shall have the same DDR-RAM connection but it seems to be missing some important signals: CAS/RAS/DQS_Div0 or is these not important when using 
the chip in simple ways? I'm a complete idiot with SDR/DDR to day.

If you could commit your whole project with all synth-specific files in a Xilinx/500E under folder that would make my day! :-)

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Scratch DDR SDRAM Controller