While this core was written for the purpose of being used with the ZipCPU, as enhanced by the Wishbnone DMA bus controller used by the ZipCPU, nothing in this core prevents it from being used with any other architecture that supports the 32-bit wishbone interface of this core. Further, since the core has been designed as a wishbone slave, it has no ability to do multiple block reads or multiple block writes.
Now that I have an initial SD Card controller working over the SPI port, I've kind of fallen in love with the simple interface it uses. I'm wondering if I can't use the same control interface for the full SD protocol. To that end, I intend to build a version of this controller that works with the full SD protocol--even integrating a card detect bit to the control register. Further, I intend to demonstrate this new interface using the peripheral module found here and the Arty board (running at 200MHz). The controller will be the ZipCPU (not yet up to 200MHz), and some form of (to be determined) O/S that provides full file access via this board. Certainly, if this controller can run at a 200MHz clock, it should never slow anything down that uses it, right?