Small 1-wire (onewire) master, with Altera tools integration

Project maintainers

Jeras, Iztok

Details

Name: sockit_owm
Created: Jul 13, 2010
Updated: Feb 16, 2011
SVN Updated: Jun 26, 2011
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved

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Other project properties

Category:Communication controller
Language:Verilog
Development status:Stable
Additional info:Design done, FPGA proven, Specification done
WishBone compliant: Yes
WishBone version: n/a
License: LGPL

Description

This IP implements the 1-wire communication protocol (http://en.wikipedia.org/wiki1-Wire).
A more detailed documentation is provided in "doc/sockit_owm.odt".

RTL features:
- small RTL, should fit into a CPLD
- Avalon MM bus, Wishbone compatible with a simple adapter
- timed reset, presence, write/read bit transfers
- overdrive
- power supply (strong pull-up)

SOPC Builder integration

Nios II EDS integration:
- port of the 1-wire open domain kit version 3.10b
- interrup driven or polling driver
- uCOS-II support (only partialy tested)

The source code and documentation are available on github:
https://github.com/jerassockit_owm