SPI Verilog Master & Slave modules

Project maintainers


Name: spi_verilog_master_slave
Created: Mar 12, 2014
Updated: Apr 30, 2019
SVN Updated: Nov 18, 2018
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 2 reported / 0 solved
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Other project properties

Category:Communication controller
Development status:Beta
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL


This Project provides SPI Mode-3 Master & Slave modules in Verilog HDL.
The data width is 8 bits. It is synthesized for Xilinx Spartan 3E, & can be clocked upto 225MHz. Maximum SPI Clock (sck) Frequency is 112MHz, which is derived from Main Clock. The scaling factors for SCK from master clock can be 2, 4, 8 & 16, which can also be reduced further.

SPI Master Module is coded in FSM (finite state machine)
The slave module is designed simply like a shift register.

The interface signals are SCLK (or SCK), MOSI, MISO and SS. SCK is the SPI Clock which is generated by the master device. MOSI is the data output of master which is the data input of slave device. MISO is slave data output which is data input of master. SS is the Slave Select active low signal which enables the slave device in the bus to be active.

TO DOWNLOAD CODE: http://opencores.orgwebsvn,listing,spi_verilog_master_slave