Srdy-Drdy Library
Project maintainers
Details
Name: srdydrdy_lib
Created: Dec 22, 2009
Updated: Apr 20, 2013
SVN Updated: May 11, 2012
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Created: Dec 22, 2009
Updated: Apr 20, 2013
SVN Updated: May 11, 2012
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star2you like it: star it!
Other project properties
Category:Library
Language:Verilog
Development status:Stable
Additional info:ASIC proven, Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: Others
Language:Verilog
Development status:Stable
Additional info:ASIC proven, Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: Others
Description
The srdy-drdy library provides a group of components all built around a common data-transfer protocol. This protocol is used in datapath applications and provides bidirectional flow control.
Components in the library provide basic timing closure, clock domain crossing, basic and advanced buffering, and some arbitration and specialized components. The components in the library have been used in multiple successful tape-outs and FPGA designs.
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