Mulcock, Andrew

srl_fifo

## Status

\- Simulated and ( 16 and 32 ) programmed into a Spartan 3 FPGA  
\- Synthesised with ISE 10.1  
  
\- looking at a generic srl fifo now ise can handle such  

## Description

Synchronous FIFO's based upon the SRL feature found in Xilinx FPGA's.  
  
Built to be small.  
  
In a Spartan 3, the 8 bit wide , 16 bit deep FIFO utilises  
19 Luts  
of which 8 are used as SRL, 11 as Logic.  

## Features

Pure VHDL, no instantiated components, all inferred  
small size


<h2 id="status">Status</h2>
<p>- Simulated and ( 16 and 32 ) programmed into a Spartan 3 FPGA<br />
- Synthesised with ISE 10.1 <br />
<br />
- looking at a generic srl fifo now ise can handle such<br />
</p>
<h2 id="description">Description</h2>
<p>Synchronous FIFO's based upon the SRL feature found in Xilinx FPGA's.<br />
<br />
Built to be small. <br />
<br />
In a Spartan 3, the 8 bit wide , 16 bit deep FIFO utilises<br />
19 Luts<br />
of which 8 are used as SRL, 11 as Logic.<br />
</p>
<h2 id="features">Features</h2>
<p>Pure VHDL, no instantiated components, all inferred<br />
small size<br />
<br />
</p>


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srl_fifo

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