Project maintainers


Name: srl_fifo
Created: Jan 2, 2008
Updated: Feb 28, 2011
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 0 solved
Star2you like it: star it!

Other project properties

Category:Memory core
Development status:Stable
Additional info:Design done
WishBone compliant: No
WishBone version: n/a
License: LGPL


- Simulated and ( 16 and 32 ) programmed into a Spartan 3 FPGA
- Synthesised with ISE 10.1

- looking at a generic srl fifo now ise can handle such


Synchronous FIFO's based upon the SRL feature found in Xilinx FPGA's.

Built to be small.

In a Spartan 3, the 8 bit wide , 16 bit deep FIFO utilises
19 Luts
of which 8 are used as SRL, 11 as Logic.


Pure VHDL, no instantiated components, all inferred
small size