Burnette, David

Kent, John

System09

I wasn't able to download the project from OpenCores. Trying variants of the URL eventually worked; I had to use:

https://opencores.org/download/System09

Rather than the link provided on the site (https://opencores.org/download/system09)

The links might also be incorrect at:

http://members.optusnet.com.au/jekent/system09/

Download Link is Broken (Case Sensitive, should be System09 not system09)

The 6809 CPU core, cpu09.vhd, has been used as the basis of a CoCo3 and in a <a href="http://www.edcheung.com/album/album07/Pinball/wpc_sound.htm">  Williams Pinball Controller .</a>

The Williams Pinball Controller fails when the FIRQ is enabled. I have written test software that exercises FIRQ and it appears to work fine for my code. The solution for the pinball controller was to set the Entire flag in the FIRQ microcode. The Entire flag causes all the processor registers to be stack on an interrupt. I have no idea why this should be necessary. Further investigation is needed. It could always be a timing issue as cpu09.vhd is not cycle accurate and is roughly 15% faster, cycle for cycle than the original 6809.

FIRQ Problems on Williams Pinball Controller

1. RTI does not test the Entire flag retrieved from Condition Codes on the stack. Instead it tests the Current Entire Flag.

2. SYNC should continue execution if an interrupt is received, but masked.

3. MUL should not affect Half carry (H), Negative (N) or Overflow (V) Flags. The Carry flag (C) should be set according to bit 7 of the result in ACCB

4. DAA should set Negative (N) and Zero (Z) flags. Overflow (V) is undefined.

5. Interrupts: int_cc_state is enumerated but not defined. Make bogus interrupts perform an RTI after stacking the registers.

6. NMIs should be mask on reset until the S Stack pointer is loaded

16th July 2006
Bugs Fixed.

1. RTI has had extra state added to test Entire flag after pulling the Condition codes off the stack

2. Sync continues execution if a masked interrupt received or performs an interrupt if the mask is clear. SYNC has not been fully tested. SYNC DOES NOT wait for the Interrupt to be asserted for 3 clock cycles, as described in the 6809 programming manual.

3. A new ALU operator has been added (alu_mul) that behaves like a 16 bit add (alu_add16), but does not affect the Half Carry (H), Negative (N) or overflow (V) flags. It sets the Carry (C) Flag to bit 7 of the result in ACCB. Note that the MUL instruction now adds the intermediate MD register or zero depending on the EA register bit from the right input of the ALU. This ensures that the Zero and Carry flags are set correctly.

4. DAA now sets Zero (Z), Negative (N)and Overflow (V) flags. The operation of the Overflow flag is not defined in the 6809 programming reference manual. I have Excusive Ored bit 7 of the original ACCA value with Bit 7 of the Decimal Adjusted result and Exclusived Ored that with the pre Decimal Adjust Carry input. This appears to do the same thing as an EF68A09P under a number of test senerios, but is by no means and exhaustive test.

5. Interrupts that have disappeared after all the registers are stacked are vectored off to the RTI state to restore the registers and return from the interrupt.

6. The S register reset control sets an interrupt mask for the NMI input. This will only occur when the CPU is reset. The NMI Mask is reset whenever the S stack pointer is loaded from the ALU or pulled off the stack. This prevents NMI's occuring before the program has time to load the stack pointer used by the interrupt to save the registers.

RTI, SYNC, MUL, DAA, INT & NMI

The CLR Instruction should reset the Overflow (V) Flag

CLR does not reset V Flag

ASR, LSR & ROR affect the overflow (V) flag on the 6800 but not the 6809.

ASR, LSR & ROR Affect V Flag

It was brought to my attention that the S stack pointer was decremented in preparation for pushing the return address before the jump address was calculated. This was a problem for indirect indexed addressing using the stack pointer.

This has been fixed in the 17th September 2005 release, by adding a bus cycle after the index address is calculated to decrement the stack pointer. Note that an additional cycle has also been added to the extended JSR instruction due to the common microcode used.

JSR [0,S] Bug

alu_tfr not completely supported

The changed source:

    case alu_ctrl is
    when alu_add8 | alu_adc  =>
        cc_out(CBIT)   <= (left(7) and right(7)) or
                          (left(7) and not out_alu(7)) or
                          (right(7) and not out_alu(7));
    when alu_sub8 | alu_sbc  =>
        cc_out(CBIT)   <= ((not left(7)) and right(7)) or
                          ((not left(7)) and out_alu(7)) or
                          (right(7) and out_alu(7));
    when alu_add16   =>
        cc_out(CBIT)   <= (left(15) and right(15)) or
                          (left(15) and not out_alu(15)) or
                          (right(15) and not out_alu(15));
    when alu_sub16   =>
        cc_out(CBIT)   <= ((not left(15)) and right(15)) or
                          ((not left(15)) and out_alu(15)) or
                          (right(15) and out_alu(15));
    when alu_ror8 | alu_lsr16 | alu_lsr8 | alu_asr8 =>
        cc_out(CBIT)   <= left(0);
    when alu_rol8 | alu_asl8 =>
        cc_out(CBIT)   <= left(7);
    when alu_lsl16   =>
        cc_out(CBIT)   <= left(15);
    when alu_com =>
        cc_out(CBIT)   <= '1';
    when alu_neg | alu_clr   =>
        cc_out(CBIT)   <= out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
                          out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0);
    when alu_daa     =>
        if ( daa_reg(7 downto 4) = "0110" ) then
            cc_out(CBIT) <= '1';
        else
            cc_out(CBIT) <= '0';
        end if;
    when alu_andcc   =>
        cc_out(CBIT)   <= left(CBIT) and cc(CBIT);
    when alu_orcc    =>
        cc_out(CBIT)   <= left(CBIT) or cc(CBIT);
    when alu_tfr   =>
        cc_out(CBIT)   <= left(CBIT); 
    when others      =>
        cc_out(CBIT)   <= cc(CBIT);
    end case;
    --
    -- Zero flag
    --
    case alu_ctrl is
    when alu_add8 | alu_sub8 |
        alu_adc | alu_sbc |
        alu_and | alu_ora | alu_eor |
        alu_inc | alu_dec |
        alu_neg | alu_com | alu_clr |
        alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
        alu_ld8 | alu_st8 | alu_sex   =>
        cc_out(ZBIT)   <= not( out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
                               out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) );
    when alu_add16 | alu_sub16 |
        alu_lsl16 | alu_lsr16 |
        alu_ld16 | alu_st16 | alu_lea =>
        cc_out(ZBIT)   <= not( out_alu(15) or out_alu(14) or out_alu(13) or out_alu(12) or
                               out_alu(11) or out_alu(10) or out_alu(9) or out_alu(8) or
                               out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
                               out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) );
    when alu_andcc   =>
        cc_out(ZBIT)   <= left(ZBIT) and cc(ZBIT);
    when alu_orcc    =>
        cc_out(ZBIT)   <= left(ZBIT) or cc(ZBIT);
    when alu_tfr   =>
        cc_out(ZBIT)   <= left(ZBIT);  
    when others      =>
        cc_out(ZBIT)   <= cc(ZBIT);
    end case;

    --
    -- negative flag
    --
    case alu_ctrl is
    when alu_add8 | alu_sub8 |
         alu_adc | alu_sbc |
         alu_and | alu_ora | alu_eor |
         alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
         alu_inc | alu_dec | alu_neg | alu_com | alu_clr |
         alu_ld8 | alu_st8 | alu_sex =>
        cc_out(NBIT) <= out_alu(7);
    when alu_add16 | alu_sub16 |
         alu_lsl16 | alu_lsr16 |
         alu_ld16 | alu_st16     =>
        cc_out(NBIT) <= out_alu(15);
    when alu_andcc    =>
        cc_out(NBIT) <= left(NBIT) and cc(NBIT);
    when alu_orcc =>
        cc_out(NBIT) <= left(NBIT) or cc(NBIT);
    when alu_tfr   =>
        cc_out(NBIT) <= left(NBIT); 
    when others   =>
        cc_out(NBIT) <= cc(NBIT);
    end case;

    --
    -- Interrupt mask flag
    --
    case alu_ctrl is
    when alu_andcc      =>
        cc_out(IBIT) <= left(IBIT) and cc(IBIT);
    when alu_orcc       =>
        cc_out(IBIT) <= left(IBIT) or cc(IBIT);
    when alu_tfr   =>
        cc_out(IBIT) <= left(IBIT); 
    when alu_seif | alu_sei =>
        cc_out(IBIT) <= '1';
    when others =>
        cc_out(IBIT) <= cc(IBIT);       -- interrupt mask
    end case;

    --
    -- Half Carry flag
    --
    case alu_ctrl is
    when alu_add8 | alu_adc =>
        cc_out(HBIT) <= (left(3)  and     right(3)) or
                        (right(3) and not out_alu(3)) or
                        (left(3)  and not out_alu(3));
    when alu_andcc      =>
        cc_out(HBIT) <= left(HBIT) and cc(HBIT);
    when alu_orcc       =>
        cc_out(HBIT) <= left(HBIT) or cc(HBIT);
    when alu_tfr   =>
        cc_out(HBIT) <= left(HBIT); 
    when others =>
        cc_out(HBIT) <= cc(HBIT);
    end case;

    --
    -- Overflow flag
    --
    case alu_ctrl is
    when alu_add8 | alu_adc  =>
        cc_out(VBIT) <= (left(7) and right(7) and (not out_alu(7))) or
                        ((not left(7)) and (not right(7)) and out_alu(7));
    when alu_sub8 | alu_sbc  =>
        cc_out(VBIT) <= (left(7) and (not right(7)) and (not out_alu(7))) or
                        ((not left(7)) and right(7) and out_alu(7));
    when alu_add16       =>
        cc_out(VBIT) <= (left(15) and right(15) and (not out_alu(15))) or
                        ((not left(15)) and (not right(15)) and out_alu(15));
    when alu_sub16       =>
        cc_out(VBIT) <= (left(15) and (not right(15)) and (not out_alu(15))) or
                        ((not left(15)) and right(15) and out_alu(15));
    when alu_inc =>
        cc_out(VBIT) <= ((not left(7)) and left(6) and left(5) and left(4) and
                         left(3) and left(2) and left(1) and left(0));
    when alu_dec | alu_neg   =>
        cc_out(VBIT) <= (left(7) and (not left(6)) and (not left(5)) and (not left(4)) and
                         (not left(3)) and (not left(2)) and (not left(1)) and (not left(0)));
    when alu_asr8=>
        cc_out(VBIT) <= left(0) xor left(7);
    when alu_lsr8 | alu_lsr16=>
        cc_out(VBIT) <= left(0);
    when alu_ror8=>
        cc_out(VBIT) <= left( 0) xor cc(CBIT);
    when alu_lsl16       =>
        cc_out(VBIT) <= left(15) xor left(14);
    when alu_rol8 | alu_asl8 =>
        cc_out(VBIT) <= left( 7) xor left(6);
    when alu_and | alu_ora | alu_eor | alu_com |
        alu_st8 | alu_st16 | alu_ld8 | alu_ld16 | alu_sex =>
        cc_out(VBIT) <= '0';
    when alu_andcc       =>
        cc_out(VBIT) <= left(VBIT) and cc(VBIT);
    when alu_orcc =>
        cc_out(VBIT) <= left(VBIT) or cc(VBIT);
    when alu_tfr   =>
        cc_out(VBIT) <= left(VBIT);  
    when others =>
        cc_out(VBIT) <= cc(VBIT);
    end case;

    case alu_ctrl is
    when alu_andcc =>
        cc_out(FBIT) <= left(FBIT) and cc(FBIT);
    when alu_orcc =>
        cc_out(FBIT) <= left(FBIT) or cc(FBIT);
    when alu_tfr   =>
        cc_out(FBIT) <= left(FBIT); 
    when alu_seif =>
        cc_out(FBIT) <= '1';
    when others =>
        cc_out(FBIT) <= cc(FBIT);
    end case;

    case alu_ctrl is
    when alu_andcc =>
        cc_out(EBIT) <= left(EBIT) and cc(EBIT);
    when alu_orcc =>
        cc_out(EBIT) <= left(EBIT) or cc(EBIT);
    when alu_tfr   =>
        cc_out(EBIT) <= left(EBIT);
    when alu_see =>
        cc_out(EBIT) <= '1';
    when alu_cle =>
        cc_out(EBIT) <= '0';
    when others =>
        cc_out(EBIT) <= cc(EBIT);
    end case;
end process;

--------------------------------------------------
Corrections committed to CVS 17th September 2005
dilbert57@opencores.org
--------------------------------------------------

alu_trf not complete

in ALU is the original

when alu_lsr16 | alu_lsr8 =>
           out_alu   <= carry_in & left(15 downto 1);   -- lsr

(carry_in is set to 0 whith alu_lsr16 and alu_lsr8)

it has to be (seperate 8 bit version)

 when alu_lsr16 =>
	   out_alu   <= '0' & left(15 downto 1); 	-- lsr
 when alu_lsr8 =>
	   out_alu   <= left(15 downto 8) & '0' & left(7 downto 1); 	-- lsr    

because bit 8 shifts into into bit 7 of the lower byte.
according the datasheet the bit that shifts in should be a zero at all times.

Motorola: 
"LSR Logical Shift Right

Description: Shifts all bits of the ACCX or M one place to the right. Bit 7 is loaded
with 0. The C bit is loaded from the least significant bit of ACCX or M."

By the way: the 6809 does not have a LSRD like the HC11

The same error is in the 16 bit version.

It appears that the same error is in the HC11 core
----------------------------------------------------
Thanks for the bug report.

This problem should only be evident on single operand instructions. When LSR8 is performed on ACCA or ACCB the left side of the ALU is used. The accumulators connect to the low 8 bits of the ALU left input and the high byte of the left ALU input is set to zero, so LSR8 will look like LSR16. 

The problem arises when single operand 8 bit shifts are performed. The 8 bit data byte to be shifted is loaded into the low half of the MD register and the low byte is sign extended into the high byte. Under this condition, the MSB will not always be zero, but may be set to the sign (Bit7) of the LSB effectively performing an Arithmetic Shift Right (ASR8) rather than a Logical Shift Right (LSR8). 

To overcome this problem I have moved LSR8 to the ASR8 and ROR8 when statement, which forces the high byte to zero. The carry_in will be the carry condition code for ROR8, it will be Bit(7) for ASR8 and will be zero for LSR8.

I have updated the code in the CVS to implement this correction. Thanks again for the bug report. I will look at the system11 code shortly althought it does not appear to be a problem as the MD register is not sign extended on the first byte fetch on CPU11.

Dilbert57.

ERROR in LSR asm operation

Non Maskable Interrupts should be masked until the S stack pointer is initialised with an LDS (Load S) , LEAS (Load Effective Address), TFR <reg>,S (Transfer to S) and EXG <reg>,S (Exchange Register with S) and EXG S,<reg> (Exchange S with regsiter). This is to prevent NMI's from interrupting the CPU before the S stack pointer is initialised.

Its probably most easily done in the register control code.

J.K.

Problem Fixed in 16th July 2006 revision

J.K.

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System09