SystemC USB1.1 IP Core :: Overview

Project maintainers


Name: usb11
Created: May 10, 2004
Updated: Jul 9, 2004
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star0you like it: star it!

Other project properties

Category:Communication controller
Development status:Stable
Additional info:Design done
WishBone compliant: No
WishBone version: n/a


This project consists of the translation of the USB 1.1 Function IP Core Verilog code and dependencies, maintained by Rudolf Usselmann, into a Synopsys CoCentric SystemC Compiler compatible SystemC code.
This project is part of the BrazilIP Fenix project.


- Written In SystemC
- Synopsys CoCentric SystemC Compiler Compatibility
- Fully Synthesisable
- 8051 Interface
- OCP Interface
- Test bench is included
- SystemC code: simulation through binary generated by the gcc
- Verilog code: simulation through tools like ModelSim or Icarus (the IP Core Verilog files may be generated by CoCentric SystemC Compiler)


- The translation is done.
- It was verified by simulation with OCP Interface (SystemC and Verilog.)
- It was verified by simulation with 8051 Interface (Verilog.)
- OCP Interface Protocol under verification.
- The hardware verification will be made (XILINX XC2V2000.)
- The XILINX TIMED SIMULATION (Verilog code generated by ISE) in ModelSim is done.


- SystemC v2.0.1 - g++ or Visual C++ Compilers - Synopsys CoCentric SystemC Compiler (optional)